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3mo agoOP

RTL & Co-design Engineer (junior)

OpenAI

San Francisco, California, US$250K – $460K Yearly
Hardware
ASIC Design
Verilog
SystemVerilog
2mo agoNV

ASIC RTL Integration and Netlisting Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100K – $189.8K Yearly
ASIC Engineering
Physical Design
ASIC
RTL
3mo agoTE

SoC Top-Level Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
SoC Engineering
SoC Physical Design
Floorplanning
3w agoNV

SOC Verification Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (Hybrid)
Hardware Engineering
ASIC Verification
RTL Design
Verilog
1mo agoNV

Senior Software Engineer, Hardware Tools and Methodology Development

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
Software Engineer
Senior Software Engineer
C++
Verilog
3w agoGR

Board Test Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
Board Test Engineering
Hardware Test
JTAG
Boundary Scan
2mo agoNV

Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
Hardware Engineering
ASIC Design
ASIC Design
Timing Analysis
3mo agoNV

Senior ASIC Timing Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$168K – $310.5K Yearly
ASIC Engineer
Timing Engineer
Static Timing Analysis (STA)
Physical Design
1mo agoTE

Static Timing Analysis (STA) Methodology Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
Static Timing Analysis (STA)
PrimeTime
3mo agoD-

Analog Design Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$155K – $250K Yearly
Analog Design
Mixed Signal Design
Analog Mixed-Signal Design
Cadence