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SystemVerilog Jobs

Browse 93 SystemVerilog jobs on Inference Jobs.

93 jobs
3w agoEtched logoET

Design Verification Engineer - Internal IP

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
3w agoEtched logoET

Design Verification Engineer - Internal IP

Etched

Austin, Texas, United States (On-site)$150K – $275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
4d agoNVIDIA logoNV

System Verification Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $218.5K Yearly
System Verification Engineering
Hardware Verification
C/C++
SystemVerilog
3w agod-Matrix logoD-

Design Verification Engineer, Senior Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3K – $260K Yearly
Design Verification
Hardware Verification
SoC Verification
UVM
3d agoNVIDIA logoNV

Senior ASIC Design Engineer - Hardware

NVIDIA

Austin, Texas, United States (On-site)$136K – $264.5K Yearly
ASIC Design
Hardware Engineering
ASIC Design
System on Chip (SoC)
6d agoGraphcore logoGR

Staff/Principal Logical Design Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
Logical Design
RTL Design
SystemVerilog
VHDL
4d agoNVIDIA logoNV

Senior Digital Design Verification Engineer - Hardware

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
Design Verification
Hardware Engineering
UVM
SystemVerilog
3d agoNVIDIA logoNV

ASIC Verification Engineer

NVIDIA

Austin, Texas, United States (Hybrid)$116K – $189.8K Yearly
ASIC Verification
Hardware Engineering
ASIC Verification
SystemVerilog
3w agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226K – $445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
3d agoNVIDIA logoNV

ASIC Design Engineer - Hardware

NVIDIA

Austin, Texas, United States (Hybrid)$116K – $218.5K Yearly
ASIC Design Engineering
Hardware Engineering
RTL Design
Verilog
3d agoNVIDIA logoNV

Senior ASIC Verification Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
ASIC Verification
Design Verification
SystemVerilog
UVM
4d agoNVIDIA logoNV

Senior ASIC Verification Engineer

NVIDIA

Durham, North Carolina, United States (On-site)$136K – $264.5K Yearly
ASIC Verification
Hardware Engineering
ASIC Verification
SystemVerilog
3w agoTenstorrent logoTE

(India) System IP Design Engineer

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
RISC-V
ASIC Design
RTL Design
Verilog
4w agoNeuralink logoNE

Digital IC Design Engineer Intern

Neuralink

Fremont, California, United States (On-site)$35 – $35 Hourly
Digital IC Design
RTL Design
SystemVerilog
C/C++
3w agoEtched logoET

RTL Intern

Etched

San Jose, California, United States (On-site)
RTL Design
ASIC Engineering
Verilog
SystemVerilog
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