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SystemVerilog Assertions Jobs

Browse 38 SystemVerilog Assertions jobs on Inference Jobs.

38 jobs
2w agod-Matrix logoD-

HW Design Verification Intern

d-Matrix

Santa Clara, California, United States (Hybrid)$30 – $60 Yearly
R&D - HW Verification
Hardware Engineering
UVM
SystemVerilog
2w agoNVIDIA logoNV

Senior Formal Verification Engineer

NVIDIA

United States or Remote (California, United States)$196K – $310.5K Yearly
Formal Verification
ASIC Verification
Formal Verification
ASIC Verification
2d agod-Matrix logoD-

Design Verification Engineer, Senior Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3K – $260K Yearly
Design Verification
Hardware Verification
SoC Verification
UVM
2d agoCerebras logoCE

Design Verification Engineer- Tile

Cerebras

United States (Remote)$120K – $240K Yearly
Design Verification
Hardware Engineering
SystemVerilog
UVM
5d agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226K – $445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
3d agoNVIDIA logoNV

SOC Verification Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (Hybrid)
Hardware Engineering
ASIC Verification
RTL Design
Verilog
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