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Clock Gating Jobs

Browse 11 Clock Gating jobs on Inference Jobs.

11 jobs
3d agoNVIDIA logoNV

ASIC Clocks Design Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100K – $166.8K Yearly
ASIC Design Engineer
Clock Design Engineer
RTL Design
Verilog
2d agoNVIDIA logoNV

Senior ASIC Design Engineer – Clocks IP

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
ASIC Design Engineer
Hardware Engineer
ASIC Design
RTL Design
3d agoNVIDIA logoNV

ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Verification
Hardware Engineering
ASIC
SystemVerilog
4w agoEtched logoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
4w agoEtched logoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
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