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Clock Gating Jobs

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3w agoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
2w agoNV

Senior Chip Design Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
ASIC Design
Hardware Engineering
ASIC Design
Pre-Silicon Design
2mo agoNV

ASIC Design Engineer, Clocks

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
VLSI Design
ASIC Design
Verilog
2mo agoNV

ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Verification
Hardware Engineering
ASIC
Design Verification
3mo agoNV

Senior Post Silicon Feature Development Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $310.5K Yearly
Hardware Engineering
Silicon Engineering
System Design
Semiconductor
3w agoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
2mo agoNV

ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Engineering
Hardware Engineering
Static Timing Analysis
Timing Convergence
1mo agoTE

Staff Design for Test STA Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
DFT Engineering
STA Engineering
Design for Test
Static Timing Analysis
3w agoNV

Senior Physical Design Engineer

NVIDIA

Tel Aviv District, Israel (On-site)
Physical Design
VLSI
Physical Design
RTL2GDS
3w agoD-

Analog Design Engineer (L4/L5)

d-Matrix

Santa Clara, California, United States (Hybrid)$155K – $250K Yearly
Analog Design
Integrated Circuit Design
Analog Mixed Signal Design
Cadence
3mo agoNV

Senior ASIC RTL Integration and Netlisting Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
ASIC Design Engineer
Physical Design Engineer
ASIC
RTL Integration