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Clock Gating Jobs

Browse 20 Clock Gating jobs on Inference Jobs.

20 jobs

2wNV

GPU Power Architect - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100k – $189.8k Yearly
Electrical Engineering
Entry Level Hardware Engineer
2wNV

Senior ASIC Power Engineer

NVIDIA

California, United States (On-site)$136k – $264.5k Yearly
ASIC Engineering
Hardware Engineering
2wNV

ASIC Design Engineer, Clocks

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Digital IC Design
2wNV

ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116k – $218.5k Yearly
ASIC Verification
Design Verification
4wNV

ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$116k – $218.5k Yearly
ASIC Engineering
Hardware Engineering
5dCE

AI Silicon Circuit Simulation Engineer

Cerebras

Sunnyvale, California, United States (On-site)
Analog Design
Circuit Design
2wNV

Senior ASIC Design and STA Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Engineering
Hardware Engineering
2wNV

ASIC RTL Integration and Netlisting Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100k – $189.8k Yearly
ASIC Engineering
Hardware Engineering
2wNV

Chiplet Physical Design Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$168k – $310.5k Yearly
ASIC Design Engineer
Chiplet Design
5dNV

Signoff Methodology Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116k – $218.5k Yearly
Hardware Engineering
Methodology Engineering
2wTE

SoC Top-Level Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100k – $500k Yearly
Hardware Engineering
Physical Design
2wNV

Senior Systems and Hardware Time Synchronization Architect

NVIDIA

Yokne'am, Northern District, Israel (On-site)
5G/6G RAN Architect
Hardware Architecture
1wNV

Senior Hardware Time Synchronization Architect

NVIDIA

Yokne'am, Northern District, Israel (On-site)
Hardware Architecture
Hardware Engineering
5dNV

Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Santa Clara, California, United States (On-site)$168k – $310.5k Yearly
ASIC Design
Electrical Engineering
2wNV

ASIC Physical Design and Timing Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116k – $218.5k Yearly
ASIC Engineer
ASIC Physical Design Engineer
2wNV

ASIC Physical Design CAD, Timing Constraint and Analysis

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Engineering
ASIC Physical Design
4dNV

Circuit Design Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Circuit Design
5dTE

Staff, Design for Test Engineer (DFT)

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
ASIC Design
DFT Engineer
4wNV

Senior Circuit Design Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168k – $264.5k Yearly
Circuit Design
Digital Design
4wNV

Physical Design Backend Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
ASIC Design
Backend Engineering

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