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Design Verification Jobs in San Jose, California, United States

Browse 24 Design Verification jobs in San Jose, California, United States on Inference Jobs.

24 jobs
2 wk. agoEtched logoET

Design Verification Engineer - SoC

Etched

San Jose, California, United States (On-site)$150–275K Yearly
Design Verification Engineering
ASIC Verification
SystemVerilog
Python
2 wk. agoEtched logoET

Design Verification Engineer - Internal IP

Etched

San Jose, California, United States (On-site)$150–275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
2 wk. agoEtched logoET

RTL Design Engineer

Etched

San Jose, California, United States (On-site)$150–275K Yearly
RTL Design Engineer
ASIC Design
RTL Design
Digital Logic
2 wk. agoEtched logoET

DV Intern

Etched

San Jose, California, United States (On-site)
Design Verification
ASIC
SystemVerilog
UVM
2 wk. agoEtched logoET

DFT (Design For Test) Engineer

Etched

San Jose, California, United States (On-site)$150–275K Yearly
DFT Engineering
ASIC Design
DFT
Scan Insertion
2 wk. agoEtched logoET

Physical Design Engineer

Etched

San Jose, California, United States (On-site)$150–275K Yearly
Physical Design Engineering
ASIC Design
Physical Design
RTL Synthesis
2 wk. agoEtched logoET

PD Intern

Etched

San Jose, California, United States (On-site)
Physical Design
ASIC Design
Physical Design
ASIC Design
2 wk. agoEtched logoET

RTL Intern

Etched

San Jose, California, United States (On-site)
RTL Design
ASIC Engineering
Verilog
SystemVerilog
2 wk. agoEtched logoET

Applied AI Engineer, Silicon Engineering

Etched

San Jose, California, United States (On-site)$150–275K Yearly
Applied AI Engineering
AI Tooling Development
Python
LLM Agents
2 wk. agoEtched logoET

Chip Simulation Software Engineer

Etched

San Jose, California, United States (On-site)$200–250K Yearly
Chip Simulation Engineer
Hardware-Software Co-Design Engineer
C++
Python
2 wk. agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226–445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
3 wk. agoTenstorrent logoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100–500K Yearly
CPU Engineering
Hardware Engineering
RISC-V
RTL Design
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