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Design Verification Engineering Jobs

Browse 103 Design Verification Engineering jobs on Inference Jobs.

103 jobs
4w agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226K – $445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
4w agod-Matrix logoD-

Design Verification Engineer, Senior Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3K – $260K Yearly
Design Verification
Hardware Verification
SoC Verification
UVM
2w agoCerebras logoCE

Design Verification Engineer

Cerebras

Bengaluru, Karnataka, India (On-site)₹8M – ₹11M Yearly
Silicon
Design Verification
SystemVerilog
UVM
3h agoEtched logoET

Design Verification Engineer - SoC

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
design-verification-engineering
ASIC Verification
SystemVerilog
Python
2w agoCerebras logoCE

Design Verification Engineer

Cerebras

Sunnyvale, California, United States (On-site)$190K – $230K Yearly
Design Verification
Silicon Engineering
SystemVerilog
UVM
3h agoEtched logoET

Design Verification Engineer - Internal IP

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
asic
Design Verification
UVM
SystemVerilog
1w agoNVIDIA logoNV

Senior DFT Verification Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
DFT Engineering
ASIC Verification
DFT
DFT Verification
4w agoCerebras logoCE

Design Verification Engineer- Tile

Cerebras

United States (Remote)$120K – $240K Yearly
Design Verification
Hardware Engineering
SystemVerilog
UVM
3h agoEtched logoET

Design Verification Engineer - SoC

Etched

Austin, Texas, United States (On-site)$150K – $275K Yearly
ASIC Design Verification
SoC Verification
SystemVerilog
Python
2w agoCerebras logoCE

Sr. Staff/Staff Design Verification Engineer

Cerebras

Sunnyvale, California, United States (On-site)$250K – $300K Yearly
Design Verification
Silicon Engineering
SystemVerilog
UVM
3h agoEtched logoET

Design Verification Engineer - Internal IP

Etched

Austin, Texas, United States (On-site)$150K – $275K Yearly
asic
Design Verification
UVM
SystemVerilog
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