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Verilog/SystemVerilog Jobs

Browse 139 Verilog/SystemVerilog jobs on Inference Jobs.

61-80 of 139 jobs
3d agoEtched logoET

Design Verification Engineer - Internal IP

Etched

Austin, Texas, United States (On-site)$150K – $275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
6d agoNVIDIA logoNV

Senior Mixed-Signal Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
Mixed Signal Design
Hardware Engineering
Mixed-Signal Circuits
CMOS
3d agoEtched logoET

Design Verification Engineer - Internal IP

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
2w agoNVIDIA logoNV

ASIC Verification Engineer

NVIDIA

Austin, Texas, United States (Hybrid)$116K – $189.8K Yearly
ASIC Verification
Hardware Engineering
ASIC Verification
SystemVerilog
2d agoCoreWeave logoCO

Senior Firmware Engineer, FPGA

CoreWeave

New York, United States (On-site)$182K – $242K Yearly
Firmware Engineering
FPGA Development
FPGA
Intel/Altera Quartus
2w agoGraphcore logoGR

Staff/Principal Logical Design Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
Logical Design
RTL Design
SystemVerilog
VHDL
3d agoEtched logoET

DFT Intern

Etched

San Jose, California, United States (On-site)
DFT Engineering
ASIC Design
DFT
Verilog
2d agoOpenAI logoOP

Senior RTL Engineer, Interconnect Design

OpenAI

San Francisco, California, United States (Hybrid)$225K – $445K Yearly
RTL Engineering
SoC Design
RTL Design
Verilog
1w agoNVIDIA logoNV

ASIC Design Engineer

NVIDIA

Bengaluru, Karnataka, India (On-site)
ASIC Design Engineering
RTL Design
RTL Design
Verilog
2w agoTenstorrent logoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100K – $500K Yearly
CPU Engineering
Hardware Engineering
RISC-V
RTL Design
4w agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226K – $445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
3d agoEtched logoET

DV Intern

Etched

San Jose, California, United States (On-site)
Design Verification
ASIC
SystemVerilog
UVM
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