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Self-timed Logic Jobs

Browse 30 Self-timed Logic jobs on Inference Jobs.

30 jobs
4w agoEtched logoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
3d agoNVIDIA logoNV

Senior ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
ASIC Engineering
Hardware Engineering
Static Timing Analysis (STA)
Timing Closure
3d agoNVIDIA logoNV

Senior Logic Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $264.5K Yearly
Senior Logic Design Engineer
FPGA Design Engineering
FPGA
CPLD
6d agoGraphcore logoGR

Staff/Principal Logical Design Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
Logical Design
RTL Design
SystemVerilog
VHDL
3d agoNVIDIA logoNV

Software R&D Engineer, Digital Logic Synthesis - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
EDA Software Engineering
RTL Synthesis
C++
RTL Design
3d agoNVIDIA logoNV

Senior Custom Circuits Timing Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
Timing Analysis
Circuit Design
NanoTime
SPICE
3d agoNVIDIA logoNV

Senior Software R&D Engineer, Digital Logic Synthesis

NVIDIA

Santa Clara, California, United States (On-site)$168K – $264.5K Yearly
EDA Software Development
RTL Synthesis
C++
RTL Synthesis
3d agoNVIDIA logoNV

Senior ASIC Physical Design Engineer, Netlisting

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
ASIC Physical Design
Physical Design Engineering
ASIC Physical Design
Netlisting
4w agoNVIDIA logoNV

Logic Design Engineer, CPU Core

NVIDIA

Yokne'am, Northern District, Israel (On-site)
ASIC Design
Logic Design
Logic Design
Microarchitecture
1w agoTenstorrent logoTE

Static Timing Analysis (STA) Methodology Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
Static Timing Analysis (STA)
Primetime
3d agoNVIDIA logoNV

Senior ASIC Design Engineer – Clocks IP

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
ASIC Design Engineer
Hardware Engineer
ASIC Design
RTL Design
3d agoNVIDIA logoNV

ASIC Clocks Design Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100K – $166.8K Yearly
ASIC Design Engineer
Clock Design Engineer
RTL Design
Verilog
3w agoEtched logoET

DFT Intern

Etched

San Jose, California, United States (On-site)
DFT Engineering
ASIC Design
DFT
Verilog
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