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RISC-V Assembly Jobs

Browse 28 RISC-V Assembly jobs on Inference Jobs.

28 jobs
1w agoTenstorrent logoTE

Risc-V Architect

Tenstorrent

Toronto, Ontario, Canada (Hybrid)
Computer Architecture
RISC-V
RISC-V
C++
1w agoTenstorrent logoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100K – $500K Yearly
CPU Engineering
Hardware Engineering
RISC-V
RTL Design
1w agoTenstorrent logoTE

RISC-V AI / HPC & Agentic Software Engineering Lead

Tenstorrent

Northern America (Remote)$100K – $500K Yearly
Software Engineering
Embedded Systems
RISC-V
C/C++
1w agoTenstorrent logoTE

Director, RISC-V Software Ecosystem

Tenstorrent

United States + 1 more (Remote)$100K – $500K Yearly
RISC-V Engineering
Software Ecosystem
RISC-V
AI Workload Porting
3w agoTenstorrent logoTE

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
CPU Verification
Design Verification
RISC-V Architecture
SystemVerilog
4d agoTenstorrent logoTE

Sr. Engineer, CPU RTL Design

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
CPU Design
RTL Design
RISC-V
RTL Design
1w agoTenstorrent logoTE

CPU Architect, Load-Store

Tenstorrent

United States (Remote)$100K – $500K Yearly
CPU Architecture
Hardware Engineering
RISC-V
CPU Architecture
2w agoTenstorrent logoTE

Sr. Engineer, Performance Infrastructure

Tenstorrent

Austin, Texas, United States (Hybrid)
RISC-V
CPU Design
RISC-V
C++
3d agoTenstorrent logoTE

(India) System IP Design Engineer

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
RISC-V
ASIC Design
RTL Design
Verilog
4d agoTenstorrent logoTE

Sr. Engineer, RTL Implementation

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RTL Implementation
CPU Design
RTL Coding
Verilog
1w agoTenstorrent logoTE

GCC Compiler Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Compiler Engineering
Software Engineering
GCC
LLVM
2w agoTenstorrent logoTE

Staff Engineer, Emulation Technical Lead

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RISC-V
CPU Verification
CPU Verification
Emulation
4w agoTenstorrent logoTE

Sr. Performance Modeling Architect

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Performance Modeling Architect
CPU Architecture
RISC-V CPU
Performance Modeling
1w agoNVIDIA logoNV

Senior ASIC Verification Engineer

NVIDIA

Beer Sheva, Southern District, Israel (On-site)
ASIC Verification
Hardware Engineering
System Verilog
UVM
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