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RISC-V Development Jobs

Browse 20 RISC-V Development jobs on Inference Jobs.

20 jobs
1w agoTenstorrent logoTE

Director, RISC-V Software Ecosystem

Tenstorrent

United States + 1 more (Remote)$100K – $500K Yearly
RISC-V Engineering
Software Ecosystem
RISC-V
AI Workload Porting
3w agoTenstorrent logoTE

Staff Engineer, Software Release and Packaging - RISC V

Tenstorrent

United States + 2 more (Remote)$100K – $500K Yearly
Release Engineering
DevOps
Linux
RISC-V
1w agoTenstorrent logoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100K – $500K Yearly
CPU Engineering
Hardware Engineering
RISC-V
RTL Design
1w agoTenstorrent logoTE

RISC-V AI / HPC & Agentic Software Engineering Lead

Tenstorrent

Northern America (Remote)$100K – $500K Yearly
Software Engineering
Embedded Systems
RISC-V
C/C++
1w agoTenstorrent logoTE

Risc-V Architect

Tenstorrent

Toronto, Ontario, Canada (Hybrid)
Computer Architecture
RISC-V
RISC-V
C++
3w agoTenstorrent logoTE

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
CPU Verification
Design Verification
RISC-V Architecture
SystemVerilog
1w agoTenstorrent logoTE

Director, RISC-V Software TPM & Ops

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
RISC-V
Technical Program Management
RISC-V
Technical Program Management
2w agoTenstorrent logoTE

Sr. Engineer, Performance Infrastructure

Tenstorrent

Austin, Texas, United States (Hybrid)
RISC-V
CPU Design
RISC-V
C++
4d agoTenstorrent logoTE

Sr. Engineer, CPU RTL Design

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
CPU Design
RTL Design
RISC-V
RTL Design
3d agoTenstorrent logoTE

(India) System IP Design Engineer

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
RISC-V
ASIC Design
RTL Design
Verilog
2w agoTenstorrent logoTE

Staff Engineer, Emulation Technical Lead

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RISC-V
CPU Verification
CPU Verification
Emulation
3w agoTenstorrent logoTE

Customer TPM, RISCV

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Technical Program Management
RISC-V
RISC-V
CPU Architecture
4d agoTenstorrent logoTE

Staff Engineer, SoC RTL Engineer

Tenstorrent

Tokyo Prefecture, Japan (Hybrid)
RTL Engineering
SoC Design
Verilog
VHDL
4d agoTenstorrent logoTE

Sr. Engineer, RTL Implementation

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RTL Implementation
CPU Design
RTL Coding
Verilog
1w agoNVIDIA logoNV

Senior ASIC Verification Engineer

NVIDIA

Beer Sheva, Southern District, Israel (On-site)
ASIC Verification
Hardware Engineering
System Verilog
UVM
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