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PLL Design Jobs

Browse 193 PLL Design jobs on Inference Jobs.

61-80 of 193 jobs

2wNV

ASIC RTL Integration and Netlisting Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100k – $189.8k Yearly
ASIC Engineering
Hardware Engineering
4dNV

Memory Mask Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
Hardware Engineering
IC Layout
1wNV

Senior Software R&D Engineer, VLSI Physical Design

NVIDIA

Santa Clara, California, United States (Hybrid)$168k – $264.5k Yearly
Algorithm Engineer
Physical Design Engineer
5dTE

Staff Design for Test Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
ASIC Engineering
Design for Test
5dNV

Tapeout Mask Design Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$104k – $207k Yearly
Layout Design
Mask Design
4wNV

Research Scientist, AI Accelerator SW HW Co-Design - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$168k – $264.5k Yearly
AI Research
ASIC Engineering
5dNV

Circuit Calibration Design Engineer

NVIDIA

臺北市, Taipei, Taiwan (On-site)
Circuit Design
Electrical Engineering
4dNV

Senior Custom Silicon Design Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Hardware Engineering
5dRA

Design Engineer (Design Systems)

Relevance AI

Sydney, New South Wales, Australia (Hybrid)
Design Engineering
Design Systems
3wNV

Low Power ASIC Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100k – $189.8k Yearly
ASIC Engineering
Design Verification
4dNV

Senior Memory Mask Designer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
IC Layout
Memory Design
3wTE

Staff Engineer, ASIC Design Methodology

Tenstorrent

Boston, Massachusetts, United States (Hybrid)$100k – $500k Yearly
ASIC Design
ASIC Engineering
3wNV

Research Scientist, Electronic Design Automation - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$168k – $264.5k Yearly
ASIC Design
Electronic Design Automation (EDA)
4dNV

Manager, Chip Design

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
ASIC Design
Chip Design
5dTE

Staff, Design for Test Engineer (DFT)

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
ASIC Design
DFT Engineer
2wNV

Senior Verification Engineer, Chip Design

NVIDIA

Yokne'am, Northern District, Israel (On-site)
ASIC Design
Chip Design
3wTE

Package Design Engineer

Tenstorrent

Toronto, Ontario, Canada (Hybrid)$100k – $500k Yearly
Electrical Engineering
Hardware Engineering
4wTE

SoC Physical Design Verification Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100k – $500k Yearly
Design Verification
Hardware Engineering
5dNV

Senior PDK Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168k – $310.5k Yearly
Electrical Engineering
Hardware Engineering
5dNV

Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Santa Clara, California, United States (On-site)$168k – $310.5k Yearly
ASIC Design
Electrical Engineering

Related searches

Hardware EngineeringASIC DesignVLSI DesignElectrical EngineeringSemiconductor EngineeringASIC EngineeringPhysical DesignChip DesignDesign VerificationHardware Verification