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HDL Jobs

Browse 38 HDL jobs on Inference Jobs.

38 jobs
3d agoNVIDIA logoNV

ASIC Design Efficiency Engineer

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Engineering
Hardware Engineering
SystemVerilog
HDL
4w agoNVIDIA logoNV

DFT Engineer - Hardware

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
DFT Engineer
Hardware Engineer
DFT
RTL Design
3d agoNVIDIA logoNV

Senior Logic Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $264.5K Yearly
Senior Logic Design Engineer
FPGA Design Engineering
FPGA
CPLD
3d agoNVIDIA logoNV

Senior ASIC Power Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
ASIC Design
Power Engineering
ASIC Design
SystemVerilog
4w agoGraphcore logoGR

DDR & HBM Validation Engineer

Graphcore

Bengaluru, Karnataka, India (On-site)
Post-Silicon Validation
Memory Validation
DDR
HBM
4w agoEtched logoET

RTL Design Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
RTL Design
RTL Development
5d agoGraphcore logoGR

Staff/Principal Logical Design Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
Logical Design
RTL Design
SystemVerilog
VHDL
3w agoEtched logoET

RTL Design Engineer

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
RTL Design Engineer
ASIC Design
RTL Design
Digital Logic
3w agoEtched logoET

Design Verification Engineer - Internal IP

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
4w agoNeuralink logoNE

Digital IC Design Engineer

Neuralink

Austin, Texas, United States (On-site)$116K – $233.8K Yearly
Brain Interfaces Hardware
Digital IC Design
SystemVerilog
C/C++
2w agoEtched logoET

Front-End CAD Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
CAD Engineer
Front-End CAD
RTL Simulation
3w agoEtched logoET

Design Verification Engineer - SoC

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
Design Verification Engineering
ASIC Verification
SystemVerilog
Python
3w agoEtched logoET

Design Verification Engineer - Internal IP

Etched

Austin, Texas, United States (On-site)$150K – $275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
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