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Clock Design Jobs

Browse 44 Clock Design jobs on Inference Jobs.

21-40 of 44 jobs
2d agoNVIDIA logoNV

SOC Design Engineer, ASIC Tools and Methodology Development

NVIDIA

Austin, Texas, United States (On-site)$136K – $218.5K Yearly
SoC Design Engineer
ASIC Design
Verilog
Python
3w agoNVIDIA logoNV

Physical Design Engineer

NVIDIA

Hsinchu, Hsinchu, Taiwan (On-site)
Physical Design
VLSI
VLSI
Physical Design
3w agoNVIDIA logoNV

Physical Design Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$136K – $218.5K Yearly
Physical Design Engineering
Hardware Engineering
VLSI Physical Design
RTL2GDS
1w agoTenstorrent logoTE

Staff Design for Test STA Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
DFT Engineering
STA Engineering
Design for Test
Static Timing Analysis
1w agoEtched logoET

Physical Design Engineer

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
Physical Design Engineering
ASIC Design
Physical Design
RTL Synthesis
1w agoEtched logoET

Physical Design Engineer

Etched

Austin, Texas, United States (On-site)$150K – $275K Yearly
ASIC Design
Physical Design Engineer
Physical Design
RTL Synthesis
3w agoNVIDIA logoNV

Software Engineer, Hardware Tools and Methodology - New College Grad 2026

NVIDIA

Santa Clara, California, United States (Hybrid)$116K – $218.5K Yearly
Software Engineer
Hardware Tools Developer
C++
Verilog
3w agoNVIDIA logoNV

Senior LPU ASIC Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
ASIC Engineering
Physical Design Engineering
Physical Design
ASIC Design
2w agoEtched logoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
7d agoEtched logoET

PD Intern

Etched

San Jose, California, United States (On-site)
Physical Design
ASIC Design
Physical Design
ASIC Design
3w agoNVIDIA logoNV

DFT Engineer - New College Grad

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
DFT Engineer
Design-for-Test Engineering
DFT
Scan Test
2w agoNVIDIA logoNV

Senior DFT Power Methodology Engineer

NVIDIA

Santa Clara, California, United States (On-site)$196K – $310.5K Yearly
DFT Engineering
Power Methodology Engineering
DFT (Design for Test)
Power Analysis
2w agoEtched logoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
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