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RTL Development Jobs

Browse 59 RTL Development jobs on Inference Jobs.

41-59 of 59 jobs
3w agoNVIDIA logoNV

Senior Modeling Architect

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
Hardware Architecture
Modeling Engineering
Hardware Modeling
SystemC
3d agoCerebras logoCE

Sr. Staff/Staff Design Verification Engineer

Cerebras

Sunnyvale, California, United States (On-site)$250K – $300K Yearly
Hardware Verification Engineering
Design Verification Engineering
SystemVerilog
DPI
1w agoNVIDIA logoNV

SoC ASIC Verification Engineer – New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100K – $189.8K Yearly
ASIC Verification
SoC Verification
C++
Object-Oriented Programming
2w agoGraphcore logoGR

SoC Architect

Graphcore

Bristol, England, United Kingdom (On-site)
Architecture
SoC Architecture
SOC Architecture
Computer Architecture
2w agoNVIDIA logoNV

Senior ASIC Verification Engineer

NVIDIA

Beer Sheva, Southern District, Israel (On-site)
ASIC Verification
Hardware Engineering
System Verilog
UVM
2w agoNVIDIA logoNV

Senior Firmware Engineer - Memory Subsystem

NVIDIA

Santa Clara, California, United States (Hybrid)$224K – $356.5K Yearly
Firmware Engineering
Embedded Systems Engineering
C/C++
Python
1w agoNVIDIA logoNV

AI Chip Design Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
AI Engineering
Hardware Engineering
Python
Verilog
6d agoNeuralink logoNE

Electrical Engineer, Robotics

Neuralink

Austin, Texas, United States (On-site)$105K – $175.5K Yearly
Electrical Engineering
Robotics
Power Electronics
FPGA Hardware Design
2w agoNVIDIA logoNV

Principal System Architect, GPU

NVIDIA

Santa Clara, California, US or Remote (United States)$272K – $431.3K Yearly
GPU Architecture
SoC Architecture
GPU Architecture
System-on-Chip (SoC) Development
3w agoNVIDIA logoNV

Senior DFT Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
DFT Engineering
Test Engineering
DFT
Scan Test Plans
2w agoEtched logoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
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