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Design Verification Jobs in United States

Browse 18 Design Verification jobs in United States on Inference Jobs.

18 jobs
2w agod-Matrix logoD-

Design Verification Engineer, Senior Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3K – $260K Yearly
Design Verification
Hardware Verification
SoC Verification
UVM
2w agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226K – $445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
2w agoCerebras logoCE

Design Verification Engineer- Tile

Cerebras

United States (Remote)$120K – $240K Yearly
Design Verification
Hardware Engineering
SystemVerilog
UVM
3d agoCerebras logoCE

Design Verification Engineer

Cerebras

Sunnyvale, California, United States (On-site)$190K – $230K Yearly
Design Verification
Silicon Engineering
SystemVerilog
UVM
3d agoCerebras logoCE

Sr. Staff/Staff Design Verification Engineer

Cerebras

Sunnyvale, California, United States (On-site)$250K – $300K Yearly
Design Verification
Silicon Engineering
SystemVerilog
UVM
4w agoTenstorrent logoTE

SoC Physical Design Verification Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
Physical Design Verification
SoC Physical Verification
DRC
4w agoTenstorrent logoTE

Staff Engineer, SoC - DFD Design Verification

Tenstorrent

Boston, Massachusetts, United States (Hybrid)$100K – $500K Yearly
Design Verification
SoC
UVM
DFT
1w agoTenstorrent logoTE

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
CPU Verification
Design Verification
RISC-V Architecture
SystemVerilog
3w agoTenstorrent logoTE

Staff Engineer, CPU Core Verification

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
CPU Core Verification
RISC-V
RISC-V
CPU Verification
1w agoNeuralink logoNE

Physical Design and Verification Engineer

Neuralink

Austin, Texas, United States (On-site)$158K – $243K Yearly
Physical Design Engineering
ASIC Design
RTL-to-GDSII
Physical Design
3w agoNeuralink logoNE

Analog IC Design and Verification Engineer

Neuralink

Fremont, California, United States (On-site)$125K – $291K Yearly
Analog IC Design
Mixed-Signal Design
CMOS Circuit Design
Mixed-Signal IC Design
4w agoEtched logoET

Physical Design Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
Physical Design
Physical Design
ASIC
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