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SystemVerilog Jobs in California, United States

Browse 22 SystemVerilog jobs in California, United States on Inference Jobs.

22 jobs
2w agod-Matrix logoD-

Design Verification Engineer, Senior Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3K – $260K Yearly
Design Verification
Hardware Verification
SoC Verification
UVM
3d agoCerebras logoCE

Sr. Staff/Staff Design Verification Engineer

Cerebras

Sunnyvale, California, United States (On-site)$250K – $300K Yearly
Design Verification
Silicon Engineering
SystemVerilog
UVM
2w agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226K – $445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
2w agoCerebras logoCE

Design Verification Engineer- Tile

Cerebras

United States (Remote)$120K – $240K Yearly
Design Verification
Hardware Engineering
SystemVerilog
UVM
3w agoNeuralink logoNE

Digital IC Design Engineer Intern

Neuralink

Fremont, California, United States (On-site)$35 – $35 Hourly
Digital IC Design
RTL Design
SystemVerilog
C/C++
3d agoCerebras logoCE

Design Verification Engineer

Cerebras

Sunnyvale, California, United States (On-site)$190K – $230K Yearly
Design Verification
Silicon Engineering
SystemVerilog
UVM
3w agoEtched logoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
3w agoNeuralink logoNE

Analog IC Design and Verification Engineer

Neuralink

Fremont, California, United States (On-site)$125K – $291K Yearly
Analog IC Design
Mixed-Signal Design
CMOS Circuit Design
Mixed-Signal IC Design
2w agoOpenAI logoOP

RTL & Codesign Engineer

OpenAI

San Francisco, California, United States (Hybrid)$225K – $445K Yearly
Hardware Engineering
RTL Design
Verilog
SystemVerilog
3w agoTenstorrent logoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100K – $500K Yearly
CPU
Hardware Engineering
RISC-V
RTL Design
1w agoTenstorrent logoTE

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
CPU Verification
Design Verification
RISC-V Architecture
SystemVerilog
3w agoEtched logoET

Emulation Software Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
Embedded Software
C++
C
3w agoTenstorrent logoTE

SOC Emulation Engineer - Hardware Emulation Infrastructure

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
SoC
Hardware Engineering
Python
C++
3w agod-Matrix logoD-

Digital Design Engineer, Micro-Architect, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$180K – $300K Yearly
R&D - HW Silicon Design
ASIC Design
Micro-architecture
RTL Design
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