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ASIC Design Jobs

Browse 77 ASIC Design jobs on Inference Jobs.

21-40 of 77 jobs
3d agoNVIDIA logoNV

ASIC Design Efficiency Engineer

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Engineering
Hardware Engineering
SystemVerilog
HDL
3d agoNVIDIA logoNV

Senior ASIC AI Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $264.5K Yearly
ASIC Engineering
AI Hardware Engineering
AI Agents
Agentic Workflows
4w agoEtched logoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
3w agoEtched logoET

ASIC Architect

Etched

San Jose, California, United States (On-site)$200K – $265K Yearly
Architecture
ASIC Architecture
ASIC Design
Computer Architecture
2d agoNVIDIA logoNV

Senior Software Engineer, ASIC Design and Verification Tools

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
ASIC Engineering
Software Engineering
C++
Python
4w agoNVIDIA logoNV

Senior Chip Design Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
ASIC Design
Hardware Engineering
ASIC Design
Pre-Silicon Design
2d agoNVIDIA logoNV

ASIC Verification Engineer

NVIDIA

Austin, Texas, United States (Hybrid)$116K – $189.8K Yearly
ASIC Verification
Hardware Engineering
ASIC Verification
SystemVerilog
4w agoNVIDIA logoNV

Senior VLSI Integration Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
VLSI
ASIC Engineering
VLSI
ASIC
4w agoNeuralink logoNE

Digital IC Design Engineer

Neuralink

Austin, Texas, United States (On-site)$116K – $233.8K Yearly
Brain Interfaces Hardware
Digital IC Design
SystemVerilog
C/C++
3d agoNVIDIA logoNV

Senior Logic Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $264.5K Yearly
Senior Logic Design Engineer
FPGA Design Engineering
FPGA
CPLD
3d agoNVIDIA logoNV

Senior ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
ASIC Engineering
Hardware Engineering
Static Timing Analysis (STA)
Timing Closure
2w agoNVIDIA logoNV

ASIC Design Engineer, High Speed IO

NVIDIA

Bengaluru, Karnataka, India (On-site)
ASIC Design
RTL Design
RTL Design
UFS
4d agoTenstorrent logoTE

Senior Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Engineering
Physical Design
ASIC Design
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