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VLSI Physical Design Jobs

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4w agoTE

Sr. RTL Design Engineer - Tensix

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RTL Design
Hardware Engineering
RTL Design
Microarchitecture
3mo agoOP

RTL & Codesign Engineer

OpenAI

San Francisco, California, United States (Hybrid)$250K – $460K Yearly
Hardware Engineering
RTL Design
Verilog
SystemVerilog
4w agoCE

AI Silicon Circuit Simulation Engineer

Cerebras

Sunnyvale, California, United States (On-site)$200K – $275K Yearly
Circuit Design
Signal Integrity
Signal Integrity
Power Delivery
2mo agoNV

Senior Circuit Design Engineer - Power Delivery

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
Analog Design
Circuit Design
Analog Circuit Design
Bandgap Reference
3mo agoNV

Senior ASIC Timing Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$168K – $310.5K Yearly
ASIC Engineer
Timing Engineer
Static Timing Analysis (STA)
Physical Design
1mo agoNV

Senior Methodology Engineer, Web Development

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $218.5K Yearly
Web Development
Software Engineering
Python
Perl
2mo agoNV

ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Engineering
Hardware Engineering
Static Timing Analysis
Timing Convergence
2mo agoNV

Senior ASIC Design Engineer - Hardware

NVIDIA

Austin, Texas, United States (Hybrid)$136K – $264.5K Yearly
ASIC Design
Hardware Engineering
ASIC Design
System-On-Chip (SOC)
3mo agoD-

FPGA Design Engineer, Senior Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$142.5K – $237.5K Yearly
R&D - HW Silicon Design
FPGA Engineering
FPGA Design
FPGA Verification
2mo agoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100K – $500K Yearly
CPU
Hardware Engineering
RISC-V
RTL Design
6d agoGR

2026 Graduate Silicon Engineer

Graphcore

Cambridge, England, United Kingdom (On-site)
Graduate Engineer
Silicon Engineer
C++
Python
1mo agoTE

Static Timing Analysis (STA) Methodology Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
Static Timing Analysis (STA)
PrimeTime
2mo agoTE

Principal Engineer, CPU System Microarchitect

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Principal Engineer
CPU Architecture
RISC-V
Microarchitecture