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RTL Logic Jobs

Browse 116 RTL Logic jobs on Inference Jobs.

116 jobs

2wOP

RTL & Co-design Engineer (junior)

OpenAI

San Francisco, California, United States (Hybrid)$250k – $460k Yearly
ASIC Design
Hardware
3wTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100k – $500k Yearly
CPU
Digital Design
2wD-

Micro-Architect / RTL Design - CPU, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$196k – $300k Yearly
ASIC Design
CPU Design
2wNV

ASIC RTL Integration and Netlisting Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100k – $189.8k Yearly
ASIC Engineering
Hardware Engineering
4wNV

Senior RTL Analysis Methodology Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $264.5k Yearly
ASIC Engineering
Hardware Engineering
3wNV

Formal Verification Engineer

NVIDIA

Bengaluru, Karnataka, India (On-site)
ASIC Verification Engineer
Design Verification Engineer
3wNV

Senior Formal Verification Engineer

NVIDIA

Gurugram, Haryana, India (On-site)
ASIC Verification
Design Verification
2wNV

Senior Formal Verification Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Verification Engineer
Design Verification Engineer
4hTE

RTL Engineer, Automotive Robotics

Tenstorrent

Germany (Remote)
ASIC Engineering
Automotive Engineering
2wGR

Silicon Logical Design Engineer - Bengaluru

Graphcore

Bengaluru, Karnataka, India (On-site)
ASIC Design
Hardware Engineering
3wNV

ASIC Design Engineer, Clocks

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Digital IC Design
1wTE

Formal Verification Lead

Tenstorrent

Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
Design Verification
Electrical Engineering
4hTE

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent

United States (Remote)$100k – $500k Yearly
ASIC Physical Design
Mixed Signal Design
2wOP

RTL & Codesign Engineer

OpenAI

San Francisco, California, United States (Hybrid)$250k – $460k Yearly
ASIC Design
Computer Architecture
1wTE

Staff Engineer, SoC - DFD Design Verification

Tenstorrent

Boston, Massachusetts, United States (Hybrid)$100k – $500k Yearly
ASIC Design Verification
DFT Engineering
4wNV

Senior Circuit Design Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168k – $264.5k Yearly
Circuit Design
Digital Design
2wNV

Senior Verification Engineer, Chip Design

NVIDIA

Yokne'am, Northern District, Israel (On-site)
ASIC Design
Chip Design
2wCE

Lead RTL Design Engineer

Cerebras

Sunnyvale, California, United States (Hybrid)$175k – $275k Yearly
ASIC Design
Chip Design
4wTE

Physical Design Flow Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
CAD Engineering
Physical Design Engineering
4wNV

Formal Equivalence Checking Methodology Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $264.5k Yearly
ASIC Verification
CAD Engineering

Related searches

Hardware EngineeringRTL DesignASIC DesignSemiconductor EngineeringVLSIASIC EngineeringFormal VerificationSilicon EngineeringVLSI DesignASIC Verification