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Gate Level Verification Jobs

Explore Gate Level Verification roles on Inference Jobs and apply today.

2mo agoNV

Senior DFX Methodology Engineer

NVIDIA

Santa Clara, California, US$136K – $218.5K Yearly
DFT Engineer
ASIC Design
DFT
JTAG
1w agoNV

Physical Design Engineer

NVIDIA

Hsinchu, Hsinchu City, Taiwan (On-site)
Physical Design
VLSI
VLSI
Physical Design
4w agoNV

Circuit Design CAD Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
CAD Engineering
Circuit Design
CAD
Circuit Design
2w agoNV

Chip Design Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
Chip Design
Hardware Engineering
RTL Design
Verification
3w agoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
3w agoNV

Senior Physical Design Engineer

NVIDIA

Tel Aviv District, Israel (On-site)
Physical Design
VLSI
Physical Design
RTL2GDS
2mo agoNV

HSIO Validation Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
Validation Engineering
Hardware Engineering
PCIe
NVLINK
2w agoNV

Senior PCIe Firmware Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
Firmware Engineering
Embedded Systems
PCIe
Firmware
7d agoD-

Post-Silicon Validation Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$155K – $258K Yearly
Post-Silicon Validation
Hardware Validation
Post-Silicon Validation
PCIe Gen5