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Digital Design Verification Jobs

Browse 47 Digital Design Verification jobs on Inference Jobs.

21-40 of 47 jobs
6d agoEtched logoET

RTL Design Engineer

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
RTL Design Engineer
ASIC Design
RTL Design
Digital Logic
1w agoNVIDIA logoNV

Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes

NVIDIA

Santa Clara, California, United States (On-site)$196K – $310.5K Yearly
Digital Design
Engineering Management
Mixed-Signal Design
High Speed I/O
2w agoNeuralink logoNE

Digital IC Design Engineer

Neuralink

Austin, Texas, United States (On-site)$116K – $233.8K Yearly
Brain Interfaces Hardware
Digital IC Design
SystemVerilog
C/C++
17h agoNVIDIA logoNV

Cell Modeling and Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100K – $189.8K Yearly
Cell Modeling
Verification Engineering
Verilog HDL
SystemVerilog
6d agoEtched logoET

DV Intern

Etched

San Jose, California, United States (On-site)
Design Verification
ASIC
SystemVerilog
UVM
3w agoNVIDIA logoNV

Senior Digital Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
Digital Design Engineering
ASIC Design
RTL Design
NVLink
4w agoGraphcore logoGR

Graduate Silicon Engineer

Graphcore

Cambridge, England, United Kingdom (On-site)
Graduate Silicon Engineering
Logical Design
C++
Python
4w agoGraphcore logoGR

2026 Graduate Silicon Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
Logical Design
Silicon Engineering
RTL
C++
1w agoNVIDIA logoNV

Senior CPU Design Engineer

NVIDIA

Hillsboro, Oregon, United States (On-site)$168K – $310.5K Yearly
CPU Design
Hardware Engineering
Micro-architecture
RTL Design
2w agoTenstorrent logoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100K – $500K Yearly
CPU Engineering
Hardware Engineering
RISC-V
RTL Design
6d agoEtched logoET

RTL Intern

Etched

San Jose, California, United States (On-site)
RTL Design
ASIC Engineering
Verilog
SystemVerilog
2w agoEtched logoET

RTL Design Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
RTL Design
RTL Development
17h agoNVIDIA logoNV

SOC Design Engineer, ASIC Tools and Methodology Development

NVIDIA

Austin, Texas, United States (On-site)$136K – $218.5K Yearly
SoC Design Engineer
ASIC Design
Verilog
Python
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