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Design Checks Jobs

Browse 57 Design Checks jobs on Inference Jobs.

57 jobs
3d agoNVIDIA logoNV

ASIC Physical Design Engineer, Netlisting - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $189.8K Yearly
ASIC Physical Design
RTL Design
ASIC Physical Design
Netlisting
3d agoNVIDIA logoNV

Senior ASIC Physical Design Engineer, Netlisting

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
ASIC Physical Design
Physical Design Engineering
ASIC Physical Design
Netlisting
2w agoGraphcore logoGR

PCB CAD Design Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
PCB Design
Hardware Engineering
PCB Design
PCB Layout
3w agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226K – $445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
3w agoEtched logoET

Design Verification Engineer - Internal IP

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
3w agoEtched logoET

Design Verification Engineer - Internal IP

Etched

Austin, Texas, United States (On-site)$150K – $275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
3w agoEtched logoET

Design Verification Engineer - SoC

Etched

Austin, Texas, United States (On-site)$150K – $275K Yearly
ASIC Design Verification
SoC Verification
SystemVerilog
Python
2w agod-Matrix logoD-

Design Verification Engineer, Senior Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3K – $260K Yearly
Design Verification
Hardware Verification
SoC Verification
UVM
1w agoNVIDIA logoNV

Physical Design Engineer

NVIDIA

Hsinchu, Hsinchu, Taiwan (On-site)
Physical Design
VLSI
VLSI
Physical Design
4w agoNVIDIA logoNV

Physical Design Backend Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
Physical Design
Backend Engineering
Physical Design
RTL2GDS
3w agoEtched logoET

Design Verification Engineer - SoC

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
Design Verification Engineering
ASIC Verification
SystemVerilog
Python
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