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Circuit Simulation Jobs

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3mo agoOP

Design Verification Engineer

OpenAI

San Francisco, California, United States (On-site)$310K – $380K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
2mo agoNV

HSIO Validation Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
Validation Engineering
Hardware Engineering
PCIe
NVLINK
5d agoGR

2026 Graduate Silicon Engineer

Graphcore

Cambridge, England, United Kingdom (On-site)
Graduate Engineer
Silicon Engineer
C++
Python
4w agoTE

Physical Design Engineer - STA

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
STA
Physical Design
2mo agoNV

Principal GPU Memory Architect

NVIDIA

Santa Clara, California, United States (On-site)$272K – $431.3K Yearly
GPU Architecture
Computer Architecture
Computer Architecture
Memory Systems
2w agoNV

Senior DFT Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
DFT Engineering
ASIC Design Engineer
DFT
RTL Implementation
2mo agoOP

Software Engineer, ChatGPT Infrastructure

OpenAI

San Francisco, California, United States (On-site)$255K – $405K Yearly
Software Engineering
Infrastructure Engineering
Distributed Systems
System Design
2mo agoNV

GPU Architecture Engineer - New College Grad 2025

NVIDIA

Santa Clara, California, United States (On-site)$124K – $241.5K Yearly
GPU Architecture
Hardware Engineering
C++
Python
2mo agoCE

Product and Test Engineer

Cerebras

Sunnyvale, California, United States (On-site)$175K – $275K Yearly
Silicon
Test Engineering
Semiconductor Testing
Wafer-scale Integration
1mo agoTE

Staff Design for Test STA Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
DFT Engineering
STA Engineering
Design for Test
Static Timing Analysis
2mo agoNV

Manager, Chip Design

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
Hardware Engineering
Engineering Management
Verification
RTL Design
3w agoNV

DFT Engineer

NVIDIA

Hyderabad, Telangana, India (Hybrid)
DFT Engineering
ASIC Design
Design for Test
Memory BIST