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ASIC Design Flow Jobs

Browse 84 ASIC Design Flow jobs on Inference Jobs.

41-60 of 84 jobs
3d agoNVIDIA logoNV

Senior ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
ASIC Engineering
Hardware Engineering
Static Timing Analysis (STA)
Timing Closure
3d agoNVIDIA logoNV

Senior Logic Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $264.5K Yearly
Senior Logic Design Engineer
FPGA Design Engineering
FPGA
CPLD
3w agoEtched logoET

ASIC Architect

Etched

San Jose, California, United States (On-site)$200K – $265K Yearly
Architecture
ASIC Architecture
ASIC Design
Computer Architecture
5d agoTenstorrent logoTE

Senior Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Engineering
Physical Design
ASIC Design
2w agoTenstorrent logoTE

Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design Engineer
ASIC Design
Physical Design
ASIC Design
3d agoNVIDIA logoNV

Senior ASIC Verification Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
ASIC Verification
Design Verification
SystemVerilog
UVM
2w agoNVIDIA logoNV

ASIC Design Engineer, High Speed IO

NVIDIA

Bengaluru, Karnataka, India (On-site)
ASIC Design
RTL Design
RTL Design
UFS
3d agoNVIDIA logoNV

Senior Physical Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
VLSI Physical Design
ASIC Design
Physical Design
VLSI
3d agoNVIDIA logoNV

Senior Digital Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
Digital Design Engineering
ASIC Design
RTL Design
NVLink
3w agoTenstorrent logoTE

Staff Engineer, SoC RTL Engineer

Tenstorrent

Tokyo Prefecture, Japan (Hybrid)
Architecture
RTL Engineering
Verilog
VHDL
3d agoNVIDIA logoNV

ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Verification
Hardware Engineering
ASIC
SystemVerilog
4w agod-Matrix logoD-

Senior Staff Engineer, CAD & Flow

d-Matrix

Santa Clara, California, United States (Hybrid)$175K – $265K Yearly
Hardware Engineering
Silicon Design and Implementation
Python
TCL Scripting
4w agoNeuralink logoNE

Digital IC Design Engineer

Neuralink

Austin, Texas, United States (On-site)$116K – $233.8K Yearly
Brain Interfaces Hardware
Digital IC Design
SystemVerilog
C/C++
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