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System-On-Chip (SOC) Design Jobs

Browse 43 System-On-Chip (SOC) Design jobs on Inference Jobs.

21-40 of 43 jobs
3d agoNVIDIA logoNV

Principal System Architect, GPU

NVIDIA

Santa Clara, California, US or Remote (United States)$272K – $431.3K Yearly
GPU Architecture
SoC Architecture
GPU Architecture
System-on-Chip (SoC) Development
5d agoTenstorrent logoTE

Sr Staff Engineer, SoC RTL Design

Tenstorrent

Toronto, Ontario, Canada (Hybrid)
ASIC Design
Digital Design
RISC-V
SoC Design
3d agoNVIDIA logoNV

SoC Product Architect, Memory Ecosystem

NVIDIA

Santa Clara, California, United States (On-site)$320K – $488.8K Yearly
SoC Architecture
Memory Architecture
DRAM
LPDDR
3d agoNVIDIA logoNV

SoC Product Architect Low Power SoC

NVIDIA

Santa Clara, California, United States (On-site)$224K – $431.3K Yearly
SoC Architecture
Product Architecture
SOC Architecture
Low-Power SoC
3d agoNVIDIA logoNV

ASIC Design Engineer - Hardware

NVIDIA

Austin, Texas, United States (Hybrid)$116K – $218.5K Yearly
ASIC Design Engineering
Hardware Engineering
RTL Design
Verilog
3w agoTenstorrent logoTE

Staff Engineer, SoC RTL Engineer

Tenstorrent

Tokyo Prefecture, Japan (Hybrid)
Architecture
RTL Engineering
Verilog
VHDL
3d agoNVIDIA logoNV

Senior Platform Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$196K – $310.5K Yearly
Platform Engineering
Hardware Engineering
Board Design
System Design
3w agoNVIDIA logoNV

SOC Verification Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (Hybrid)
Hardware Engineering
ASIC Verification
RTL Design
Verilog
4w agoNVIDIA logoNV

ASIC Design Engineer

NVIDIA

Bengaluru, Karnataka, India (On-site)
ASIC Design Engineering
RTL Design
RTL Design
Verilog
2w agod-Matrix logoD-

SoC Architect

d-Matrix

Santa Clara, California, United States (Hybrid)$175K – $265K Yearly
SoC Architecture
AI Hardware Architecture
SOC Architecture
AI SoC Architecture
3d agoNVIDIA logoNV

Senior Digital Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
Digital Design Engineering
ASIC Design
RTL Design
NVLink
4w agoNeuralink logoNE

Digital IC Design Engineer Intern

Neuralink

Fremont, California, United States (On-site)$35 – $35 Hourly
Digital IC Design
RTL Design
SystemVerilog
C/C++
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