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Timing Closure Jobs

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4w agoTE

Senior Engineer, Physical Design – EMIR

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design Engineer
Silicon Engineering
Physical Design
EMIR analysis
3mo agoOP

Physical Design Engineer

OpenAI

San Francisco, California, United States (On-site)$310K – $460K Yearly
Hardware
Physical Design
Physical Design
Silicon Implementation
3mo agoTE

SoC Top-Level Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
SoC Engineering
SoC Physical Design
Floorplanning
4d agoTE

Sr Staff Engineer, SoC RTL Design

Tenstorrent

Toronto, Ontario, Canada (Hybrid)
ASIC Design
Digital Design
RISC-V
SoC Design
2w agoNV

Logic Design Engineer, CPU Core

NVIDIA

Yokne'am, Northern District, Israel (On-site)
ASIC Design
Logic Design
Logic Design
Microarchitecture
1mo agoOP

Forward Deployed Engineer - Semiconductor

OpenAI

San Francisco, California, United States (Hybrid)$162K – $302K Yearly
Forward Deployed Engineering
Solutions Engineering
Semiconductor
Chip Design
2mo agoNV

ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Engineering
Hardware Engineering
Static Timing Analysis
Timing Convergence
1mo agoTE

Static Timing Analysis (STA) Methodology Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
Static Timing Analysis (STA)
PrimeTime
1mo agoTE

Staff Design for Test STA Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
DFT Engineering
STA Engineering
Design for Test
Static Timing Analysis
3mo agoNV

Senior ASIC Timing Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$168K – $310.5K Yearly
ASIC Engineer
Timing Engineer
Static Timing Analysis (STA)
Physical Design
1mo agoNV

Senior Verification Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $218.5K Yearly
Design Verification
ASIC Verification
SystemVerilog
UVM
2mo agoNV

Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
Hardware Engineering
ASIC Design
ASIC Design
Timing Analysis
3mo agoTE

Chiplet Physical Design Engineer

Tenstorrent

東京都, Tokyo Prefecture, Japan (Hybrid)
Physical Design
VLSI
Physical Design
Synthesis