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Static Timing Analysis (STA) Jobs

Browse 72 Static Timing Analysis (STA) jobs on Inference Jobs.

41-60 of 72 jobs

6dCE

AI Silicon Circuit Simulation Engineer

Cerebras

Sunnyvale, California, United States (On-site)
Analog Design
Circuit Design
6dTE

Formal Verification Lead

Tenstorrent

Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
Design Verification
Electrical Engineering
6dTE

Staff/Sr. Staff Engineer, Diagnostic Development

Tenstorrent

Toronto, Ontario, Canada (Hybrid)$100k – $500k Yearly
ASIC Verification
Diagnostic Engineering
3wD-

Principal ATE Test Engineer

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3k – $268.8k Yearly
ATE Test Engineering
Hardware Engineering
2wNV

ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116k – $218.5k Yearly
ASIC Verification
Design Verification
2wNV

Architect - Performance Verification and Analysis

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
Computer Architecture
GPU Architecture
2wNV

Senior Systems and Hardware Time Synchronization Architect

NVIDIA

Yokne'am, Northern District, Israel (On-site)
5G/6G RAN Architect
Hardware Architecture
4dGR

Silicon Verification Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
ASIC Verification
Hardware Verification
4dTE

Sr. Staff Product Development Engineer - Test Methodology Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
Hardware Engineering
Product Development Engineering
1wNV

Senior Hardware Time Synchronization Architect

NVIDIA

Yokne'am, Northern District, Israel (On-site)
Hardware Architecture
Hardware Engineering
2wTE

Staff Engineer Design Verification

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
ASIC Verification Engineer
Design Verification Engineer
2wD-

Post-Silicon Validation Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$155k – $258k Yearly
ASIC Verification
Embedded Systems
2wNV

Senior Verification Engineer, Performance

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
CPU Design
Hardware Engineering
3wNV

DFT ATPG Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
ASIC Design
DFT Engineering
4wGR

Staff Post‑Silicon Lab Characterisation Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
Hardware Engineering
Post-Silicon Validation
6dNV

Senior Performance Verification Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136k – $264.5k Yearly
CPU Verification
Hardware Engineering
4wTE

SoC Physical Design Verification Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100k – $500k Yearly
Design Verification
Hardware Engineering
2wD-

Design Verification Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3k – $260k Yearly
ASIC Verification
Design Verification
6dTE

Staff Engineer, SoC - DFD Design Verification

Tenstorrent

Boston, Massachusetts, United States (Hybrid)$100k – $500k Yearly
ASIC Design Verification
DFT Engineering
2dTE

Verification Engineer

Tenstorrent

Japan (Hybrid)
Architecture
ASIC Verification

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Hardware EngineeringSemiconductor EngineeringASIC VerificationDesign VerificationSilicon ValidationTest EngineeringPerformance EngineeringSoC VerificationDFT EngineeringElectrical Engineering