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SEL RTAC Jobs

Browse 54 SEL RTAC jobs on Inference Jobs.

54 jobs
1w agoTenstorrent logoTE

Physical Design Engineer - STA

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
STA
Physical Design
5d agoNVIDIA logoNV

STA Engineer

NVIDIA

Yokneam, Haifa District, Israel (On-site)
STA Engineer
Physical Design Engineer
Static Timing Analysis
DFT
2w agoCoreWeave logoCO

Fleet Engineering Project Manager, Data Center

CoreWeave

Dallas, Texas, United States (On-site)$99K – $132K Yearly
Fleet Engineering
Data Center Operations
RMA
Data Center Operations
6d agoNVIDIA logoNV

Senior SMTA Engineer

NVIDIA

Guadalajara, Jalisco, Mexico (On-site)
SMTA Engineering
Manufacturing Engineering
SMTA
PCBA
1d agoOpenAI logoOP

Senior RTL Engineer, Interconnect Design

OpenAI

San Francisco, California, United States (Hybrid)$225K – $445K Yearly
RTL Engineering
SoC Design
RTL Design
Verilog
1w agoEtched logoET

RTL Design Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
RTL Design
RTL Development
1w agoEtched logoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
4w agoEtched logoET

Front-End CAD Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
CAD Engineer
Front-End CAD
RTL Simulation
3w agoTenstorrent logoTE

Static Timing Analysis (STA) Methodology Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
Static Timing Analysis (STA)
Primetime
4d agoTenstorrent logoTE

Staff Engineer, SoC RTL Engineer

Tenstorrent

Tokyo Prefecture, Japan (Hybrid)
RTL Engineering
SoC Design
Verilog
VHDL
2w agoNVIDIA logoNV

Circuit Design Engineer - Standard Cell

NVIDIA

Santa Clara, California, United States (On-site)$116K – $189.8K Yearly
Circuit Design Engineering
VLSI Engineering
Spice Simulation
Standard Cell Circuit Design
2w agoNVIDIA logoNV

Senior ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
ASIC Engineering
Hardware Engineering
Static Timing Analysis (STA)
Timing Closure
2w agoAnthropic logoAN

Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic

San Francisco, California, United States (On-site)$500K – $850K Yearly
AI Research & Engineering
Chip Design
Reinforcement Learning
RTL Design
3d agoTenstorrent logoTE

(India) System IP Design Engineer

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
RISC-V
ASIC Design
RTL Design
Verilog
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