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RTL Architecture Jobs

Browse 49 RTL Architecture jobs on Inference Jobs.

49 jobs
1w agoEtched logoET

RTL Design Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
RTL Design
RTL Development
4d agoTenstorrent logoTE

Staff Engineer, SoC RTL Engineer

Tenstorrent

Tokyo Prefecture, Japan (Hybrid)
RTL Engineering
SoC Design
Verilog
VHDL
2d agoEtched logoET

RTL Design Engineer

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
RTL Design Engineer
ASIC Design
RTL Design
Digital Logic
1d agoOpenAI logoOP

Senior RTL Engineer, Interconnect Design

OpenAI

San Francisco, California, United States (Hybrid)$225K – $445K Yearly
RTL Engineering
SoC Design
RTL Design
Verilog
1w agoTenstorrent logoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100K – $500K Yearly
CPU Engineering
Hardware Engineering
RISC-V
RTL Design
2w agoTenstorrent logoTE

Sr Staff Engineer, SoC RTL Design

Tenstorrent

Toronto, Ontario, Canada (Hybrid)
ASIC Design
Digital Design
RISC-V
SoC Design
4d agoTenstorrent logoTE

Sr. Engineer, RTL Implementation

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RTL Implementation
CPU Design
RTL Coding
Verilog
4d agoTenstorrent logoTE

Sr. Engineer, CPU RTL Design

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
CPU Design
RTL Design
RISC-V
RTL Design
3d agoTenstorrent logoTE

(India) System IP Design Engineer

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
RISC-V
ASIC Design
RTL Design
Verilog
2w agoNVIDIA logoNV

Software R&D Engineer, RTL Optimization Tools

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $218.5K Yearly
CAD Software Development
EDA Tools Development
C++
RTL Design
3w agoNVIDIA logoNV

Chip Design Engineer

NVIDIA

Tel Aviv District, Israel (On-site)
Chip Design
Hardware Engineering
RTL Design
Verification
2d agoEtched logoET

RTL Intern

Etched

San Jose, California, United States (On-site)
RTL Design
ASIC Engineering
Verilog
SystemVerilog
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