Inference Jobs logo

Inference Jobs

  1. Home
  2. Jobs
  3. On-chip Scan Compression

On-chip Scan Compression Jobs

Browse 65 On-chip Scan Compression jobs on Inference Jobs.

41-60 of 65 jobs

3wD-

Principal ATE Test Engineer

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3k – $268.8k Yearly
ATE Test Engineering
Hardware Engineering
1wTE

Power Architect, AI Data Center Chiplets

Tenstorrent

Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
Architecture
Chip Design
2wD-

ML Compiler Architect, Senior Principal

d-Matrix

Toronto, Ontario, Canada (Hybrid)
Compiler Engineering
Machine Learning Compiler
2wOP

Reliability/DFX Engineer

OpenAI

San Francisco, California, United States (On-site)$285k – $460k Yearly
ASIC Design
DFX
1wNV

Senior SoC Methodology Architect, VLSI Physical Design

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $218.5k Yearly
Engineering
Hardware Engineering
4wTE

Package Design Engineer

Tenstorrent

Toronto, Ontario, Canada (Hybrid)$100k – $500k Yearly
Electrical Engineering
Hardware Engineering
2wNV

Circuit Silicon Correlation DFT Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Design
DFT Engineering
4wTE

Chiplet Physical Design Engineer

Tenstorrent

東京都, Tokyo Prefecture, Japan (Hybrid)
Hardware Engineering
IC Design
1wFI

Senior Hardware Failure Analysis Engineer

Figure

San Jose, California, United States (On-site)
Failure Analysis
Hardware Engineering
2wTE

Chiplet Physical Design Engineer

Tenstorrent

United States (Remote)$100k – $500k Yearly
ASIC Design Engineer
Hardware Engineer
2wNV

Chiplet Physical Design Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$168k – $310.5k Yearly
ASIC Design Engineer
Chiplet Design
7dNV

Senior Test Methodology Engineer

NVIDIA

Santa Clara, California, United States (On-site)$132k – $253k Yearly
DFT Engineering
Hardware Engineering
2wNV

Senior NPI Engineer, Chip

NVIDIA

Yokne'am, Northern District, Israel (On-site)
Hardware Engineering
NPI Engineering
1wNV

Tapeout Mask Design Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$104k – $207k Yearly
Layout Design
Mask Design
5dNV

DFT Verification Engineer

NVIDIA

臺北市, Taipei, Taiwan (On-site)
ASIC Verification
Design Verification
2wNV

Senior Patent Counsel

NVIDIA

Santa Clara, California, United States (On-site)$224k – $356.5k Yearly
Corporate Counsel
IP Counsel
1wNV

Senior Package Layout Engineer - Hardware

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Design
Electrical Engineering
2wPO

Chief Mechanical Engineer

Poolside

Fort Stockton, Texas, United States (On-site)
Critical Facilities
Data Center
2wNV

Senior Machine Learning Applications and Compiler Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$152k – $287.5k Yearly
AI Compiler Engineer
AI Infrastructure Engineer
1wNV

RTL Design Engineer, DFT

NVIDIA

Yokneam Ilit, Northern District, Israel (On-site)
ASIC Design
DFT Engineering

Related searches

Hardware EngineeringASIC DesignDFT EngineeringPhysical DesignSemiconductor EngineeringVLSI DesignElectrical EngineeringSemiconductor ManufacturingTest EngineeringASIC Design Engineer