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Constrained-Random Verification Jobs

Explore Constrained-Random Verification roles on Inference Jobs and apply today.

2w agoNV

Physical Design Backend Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
Physical Design
Backend Engineering
Physical Design
RTL2GDS
2w agoNV

Chip Design Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
Chip Design
Hardware Engineering
RTL Design
Verification
1w agoNV

Senior System Validation Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
System Validation
Hardware Validation
Python
Perl
3mo agoOP

Fraud & Risk Analyst

OpenAI

San Francisco, California, United States (Hybrid)$280K – $280K Yearly
Risk Management
Fraud Investigation
Fraud Investigations
Identity Verification
3w agoET

Front-End CAD Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
CAD Engineer
Front-End CAD
RTL Simulation
4w agoAI

Application Security Engineer

Applied Intuition

Sunnyvale, California, United States (On-site)$150K – $220K Yearly
Application Security
Product Security
Application Security
Product Security
1w agoNV

Physical Design Engineer

NVIDIA

Hsinchu, Hsinchu City, Taiwan (On-site)
Physical Design
VLSI
VLSI
Physical Design
3w agoET

PCB Hardware Validation Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
Hardware Engineering
PCB
PCIe
2w agoNV

Senior Physical Design Backend Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
Physical Design
Backend Engineering
Physical Design
RTL2GDS
2w agoAN

Research Engineer – Cybersecurity RL

Anthropic

San Francisco, California, United States (Hybrid)$300K – $405K Yearly
AI Research & Engineering
Cybersecurity
Cybersecurity
Reinforcement Learning
2mo agoNV

Senior DFX Methodology Engineer

NVIDIA

Santa Clara, California, US$136K – $218.5K Yearly
DFT Engineer
ASIC Design
DFT
JTAG
1mo agoNV

Circuit Design Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $189.8K Yearly
Circuit Design
Hardware Engineering
Standard Cell Design
ROM Design
1mo agoCE

DVT- Technical Lead

Cerebras

Sunnyvale, California, United States (On-site)$175K – $275K Yearly
Electrical Engineering
Hardware Engineering
DVT
Root Cause Analysis
2mo agoD-

Analog IC Design Intern

d-Matrix

Santa Clara, California, United States (Hybrid)$30 – $60 Yearly
Electrical Engineering
Analog IC Design
Analog IC Design
Cadence Virtuoso
2w agoNV

Senior DFT Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
DFT Engineering
ASIC Design Engineer
DFT
RTL Implementation