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Chip-Package Co-Design Jobs

Browse 273 Chip-Package Co-Design jobs on Inference Jobs.

121-140 of 273 jobs

2wD-

Post-Silicon Validation Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$155k – $258k Yearly
ASIC Verification
Embedded Systems
1wNV

Senior Memory Mask Designer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
IC Layout
Memory Design
1wNV

CAD Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$116k – $218.5k Yearly
CAD Engineering
Design Automation
2wPO

Chief Mechanical Engineer

Poolside

Fort Stockton, Texas, United States (On-site)
Critical Facilities
Data Center
1wTE

Memory Architect

Tenstorrent

North America + 1 more (Remote)$100k – $500k Yearly
Chip Architecture
Hardware Architecture
2wD-

Senior Runtime Systems Engineer

d-Matrix

Santa Clara, California, United States (Hybrid)
Embedded Systems
Firmware Engineering
1wTE

Staff Mixed Signal Design Engineer, Silicon Validation

Tenstorrent

Santa Clara, California, United States (On-site)$100k – $500k Yearly
Electrical Engineering
Hardware Engineering
3wCO

Staff Power Engineer

CoreWeave

Livingston, New Jersey, United States (Hybrid)$188k – $275k Yearly
Data Center Engineering
Electrical Engineering
1wOP

Product Manufacturing Engineer

OpenAI

San Francisco, California, United States (Hybrid)$123k – $285k Yearly
Hardware Engineering
Manufacturing Engineering
1wNV

Memory Mask Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
Hardware Engineering
IC Layout
1wTE

GCC Compiler Engineer

Tenstorrent

Santa Clara, California, United States (On-site)$100k – $500k Yearly
AI Engineering
Compiler Engineering
2wNV

Senior Embedded Software Developer

NVIDIA

Santa Clara, California, United States (On-site)$184k – $356.5k Yearly
C Programming
Embedded Software Engineering
3wTE

CPU Design Verification Technical Lead

Tenstorrent

United States (Hybrid)$100k – $500k Yearly
CPU Verification
Design Verification
2wNV

Principal System Architect, GPU

NVIDIA

Santa Clara, California, United States (On-site)$272k – $431.3k Yearly
Chip Architecture
GPU Engineering
3wNV

Senior Mask Layout Design Engineer

NVIDIA

新竹市, Hsinchu City, Taiwan (Hybrid)
Analog Layout
IC Layout
1wCE

CoDesign & NextGen - New College Grad

Cerebras

Sunnyvale, California, United States (On-site)$145k – $155k Yearly
Hardware Engineer
Kernel Development
3wCR

Infrastructure Design Engineer

Crusoe

Dallas, Texas, United States (Hybrid)$160k – $195k Yearly
Data Center Engineer
Data Center Operations
1wNV

Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Santa Clara, California, United States (On-site)$168k – $310.5k Yearly
ASIC Design
Electrical Engineering
1wGR

Staff Engineering Program Support

Graphcore

Austin, Texas, United States (On-site)
Engineering Program Management
Manufacturing Support
4wTE

Staff Engineer, ASIC Design Methodology

Tenstorrent

Boston, Massachusetts, United States (Hybrid)$100k – $500k Yearly
ASIC Design
ASIC Engineering

Related searches

Hardware EngineeringSemiconductor EngineeringVLSI DesignElectrical EngineeringEmbedded SystemsIC LayoutMemory DesignSilicon ValidationASIC DesignChip Architecture