Chip-Package Co-Design Jobs
Browse 282 Chip-Package Co-Design jobs on Inference Jobs.
282 jobs
7dOP
Advanced Packaging Technologist
OpenAI
San Francisco, California, United States (On-site)$266k – $445k Yearly
3wNV
Senior Package Layout Engineer - Hardware
NVIDIA
Santa Clara, California, United States (Hybrid)$136k – $258.8k Yearly
7dTE
Sr. Engineer, SoC Design Verification – AI/ML Accelerator Chiplets
Tenstorrent
Toronto, Ontario, Canada (Hybrid)
4dNV
Senior System-Manufacturing Co-Design Engineer
NVIDIA
Santa Clara, California, United States (Hybrid)$168k – $310.5k Yearly
4dNV
CPO Integration Engineer - LPU Packaging
NVIDIA
Santa Clara, California, United States (On-site)$140k – $276k Yearly
3wTE
SoC Top-Level Physical Design Engineer
Tenstorrent
Austin, Texas, United States (Hybrid)$100k – $500k Yearly
5dCE
Advanced Packaging Technologist & Lead
Cerebras
Sunnyvale, California, United States (On-site)$175k – $275k Yearly
7dTE
Power Architect, AI Data Center Chiplets
Tenstorrent
Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
2wNV
Chip Engineering Operations Program Manager
NVIDIA
Santa Clara, California, United States (On-site)$136k – $258.8k Yearly
2wNV
Chiplet Physical Design Engineer
NVIDIA
Westford, Massachusetts, United States (On-site)$168k – $310.5k Yearly
7dNV
Senior SoC Methodology Architect, VLSI Physical Design
NVIDIA
Santa Clara, California, United States (Hybrid)$136k – $218.5k Yearly
7dNV
Senior System Co-Design Engineer - Speed and Reliability
NVIDIA
Santa Clara, California, United States (Hybrid)$136k – $264.5k Yearly