Inference Jobs logo

Inference Jobs

  1. Home
  2. Jobs
  3. Chip-Package Co-Design

Chip-Package Co-Design Jobs

Browse 273 Chip-Package Co-Design jobs on Inference Jobs.

81-100 of 273 jobs

1wNV

Senior PDK Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168k – $310.5k Yearly
Electrical Engineering
Hardware Engineering
1wTE

Physical Design Engineer - STA

Tenstorrent

Austin, Texas, United States (Hybrid)$100k – $500k Yearly
ASIC Design
Hardware Engineering
1wNV

CAD Engineer, Physical Design - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100k – $189.8k Yearly
CAD Engineering
Electrical Engineering
2wNV

CAD Layout Design Engineer

NVIDIA

Bengaluru, Karnataka, India (On-site)
Analog Layout
CAD Engineering
1wGR

Hardware Development Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
Electrical Engineering
Hardware Engineering
1wNV

Physical Design Engineer

NVIDIA

新竹市, Hsinchu City, Taiwan (On-site)
ASIC Design
Hardware Engineering
2wNV

Senior ASIC Design and STA Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Engineering
Hardware Engineering
1wGR

2026 Graduate Silicon Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
ASIC Design
Graduates
1wTE

Physical Design Engineer, Multi Voltage / Power Grid Construction

Tenstorrent

Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
Hardware Engineering
IC Design
1wGR

2026 Graduate Silicon Engineer

Graphcore

Cambridge, England, United Kingdom (On-site)
ASIC Design
Graduate Engineer
1wNV

Senior Calibre CAD Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $264.5k Yearly
CAD Engineering
Design Automation
1wNV

Circuit Design Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Circuit Design
4wD-

HW Engineering Intern - PCB Layout Automation & AI Tooling

d-Matrix

Santa Clara, California, United States (Hybrid)$30 – $59 Hourly
Electrical Engineering
Engineering Internship
1dTE

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent

United States (Remote)$100k – $500k Yearly
ASIC Physical Design
Mixed Signal Design
4wTE

Physical Design Flow Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
CAD Engineering
Physical Design Engineering
2wNV

Electronic Design Automation Intern - 2026

NVIDIA

新竹市, Hsinchu City, Taiwan (On-site)
EDA Engineer
Electronic Design Automation Intern
3wNV

ASIC Physical Design CAD, Timing Constraint and Analysis

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Engineering
ASIC Physical Design
3wNV

Senior Physical Methodology Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Design
Design Methodology
6dNV

Senior Manufacturing Technologies and Process Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
Hardware Engineering
Manufacturing Engineering
1wNV

Signoff Methodology Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116k – $218.5k Yearly
Hardware Engineering
Methodology Engineering

Related searches

Hardware EngineeringPhysical DesignVLSI DesignSemiconductor EngineeringASIC DesignCAD EngineeringElectrical EngineeringVLSIPCB DesignASIC Engineering