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ASIC Performance Modeling Jobs

Browse 383 ASIC Performance Modeling jobs on Inference Jobs.

41-60 of 383 jobs

2wNV

ASIC RTL Integration and Netlisting Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100k – $189.8k Yearly
ASIC Engineering
Hardware Engineering
3wNV

Senior ASIC Design Engineer

NVIDIA

Canada, Remote, Canada (Hybrid)C$155k – C$245k Yearly
ASIC Design
Digital Design
1wTE

Staff Design for Test Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100k – $500k Yearly
ASIC Engineering
Design for Test
3wNV

Low Power ASIC Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100k – $189.8k Yearly
ASIC Engineering
Design Verification
3wNV

Senior ASIC Power Engineer

NVIDIA

California, United States (On-site)$136k – $264.5k Yearly
ASIC Engineering
Hardware Engineering
1wCE

3D Physical Design Engineer

Cerebras

Sunnyvale, California, United States (On-site)$150k – $270k Yearly
3D Integration
ASIC Design
1wNV

RTL Design Engineer, DFT

NVIDIA

Yokneam Ilit, Northern District, Israel (On-site)
ASIC Design
DFT Engineering
1wNV

Senior Custom Silicon Design Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Hardware Engineering
3wNV

Senior GPU Floorplan Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Physical Design
Floorplanning
3wNV

Chip Engineering Operations Program Manager

NVIDIA

Santa Clara, California, United States (On-site)$136k – $258.8k Yearly
Chip Engineering
Engineering Program Manager
2wNV

Senior Technical Program Manager – VLSI

NVIDIA

Santa Clara, California, United States (On-site)$168k – $322k Yearly
ASIC Program Manager
Engineering Program Manager
4wNV

Senior RTL Analysis Methodology Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $264.5k Yearly
ASIC Engineering
Hardware Engineering
1wNV

Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Santa Clara, California, United States (On-site)$168k – $310.5k Yearly
ASIC Design
Electrical Engineering
1dTE

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent

United States (Remote)$100k – $500k Yearly
ASIC Physical Design
Mixed Signal Design
2wD-

Micro-Architect / RTL Design - CPU, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$196k – $300k Yearly
ASIC Design
CPU Design
3wD-

Digital Design Engineer, Micro-Architect, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$180k – $300k Yearly
ASIC Design
Digital IC Design
2wNV

Principal Digital Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$232k – $368k Yearly
ASIC Engineer
Digital Design Engineer
1wTE

Sr. Engineer, SoC Design Verification – AI/ML Accelerator Chiplets

Tenstorrent

Toronto, Ontario, Canada (Hybrid)
ASIC Verification
Design Verification
3wCE

Lead RTL Design Engineer

Cerebras

Sunnyvale, California, United States (Hybrid)$175k – $275k Yearly
ASIC Design
Chip Design
1wTE

Senior Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100k – $500k Yearly
ASIC Design
Hardware Engineering

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Hardware EngineeringASIC DesignRTL DesignASIC EngineeringPhysical DesignSemiconductor EngineeringElectrical EngineeringVLSIVLSI DesignASIC Physical Design