Inference Jobs logo

Inference Jobs

  1. Home
  2. Jobs
  3. ASIC Design Verification

ASIC Design Verification Jobs

Explore ASIC Design Verification roles on Inference Jobs and apply today.

1mo agoNV

Senior Software Engineer, Hardware Tools and Methodology Development

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
Software Engineer
Senior Software Engineer
C++
Verilog
2mo agoNV

Senior Post Silicon Validation Engineer

NVIDIA

Santa Clara, California, United States (On-site)$196K – $368K Yearly
Hardware Engineering
Semiconductor Engineering
SoC
GPU
4w agoGR

Senior SoC Architect

Graphcore

Bristol, England, United Kingdom (On-site)
Silicon Architecture
SoC Architecture
SoC Architecture
Semiconductor
2mo agoNV

Senior Technical Program Manager – VLSI

NVIDIA

Santa Clara, California, United States (On-site)$168K – $322K Yearly
Technical Program Manager
Engineering Program Manager
VLSI
Semiconductor Design
3mo agoTE

Chiplet Physical Design Engineer

Tenstorrent

東京都, Tokyo Prefecture, Japan (Hybrid)
Physical Design
VLSI
Physical Design
Synthesis
1mo agoCE

Director of Engineering

Cerebras

Sunnyvale, California, United States (Hybrid)$310K – $330K Yearly
Engineering Management
Hardware Engineering
Python
Verilog
3w agoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
3mo agoNV

Senior Mask Layout Design Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$132K – $207K Yearly
Mask Design
Physical Design
Mixed-Signal Design
CMOS
2w agoGR

Staff Post Silicon Validation Engineer (Bringup)

Graphcore

Austin, Texas, United States (On-site)$191.1K – $258.5K Yearly
Silicon Validation
Hardware Engineering
C/C++
Python
2w agoNV

DFT Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
DFT Engineering
Hardware Engineering
DFT
ATPG
3mo agoNV

Implementation Methodology Engineer - GPU

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
VLSI Engineering
Hardware Engineering
Synthesis
Formal Equivalence Checking