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Verilog Jobs in United States

Browse 16 Verilog jobs in United States on Inference Jobs.

16 jobs
4w agod-Matrix logoD-

Digital Design Engineer, Micro-Architect, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$180K – $300K Yearly
R&D - HW Silicon Design
ASIC Design
Micro-architecture
RTL Design
4w agoEtched logoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
3w agoNeuralink logoNE

Analog IC Design and Verification Engineer

Neuralink

Fremont, California, United States (On-site)$125K – $291K Yearly
Analog IC Design
Mixed-Signal Design
CMOS Circuit Design
Mixed-Signal IC Design
2w agoOpenAI logoOP

RTL & Codesign Engineer

OpenAI

San Francisco, California, United States (Hybrid)$225K – $445K Yearly
Hardware Engineering
RTL Design
Verilog
SystemVerilog
4w agoTenstorrent logoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100K – $500K Yearly
CPU
Hardware Engineering
RISC-V
RTL Design
3w agoTenstorrent logoTE

Sr. Engineer, RTL Implementation

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RTL Implementation
CPU Design
RTL Coding
Verilog
3w agoTenstorrent logoTE

Sr. Engineer, CPU RTL Design

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
CPU Design
RTL Design
RISC-V
RTL Design
2w agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226K – $445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
4w agoEtched logoET

Emulation Software Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
Embedded Software
C++
C
4w agoTenstorrent logoTE

Staff Engineer, Emulation Technical Lead

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RISC V
CPU Verification
CPU Verification
Emulation
1w agoNeuralink logoNE

Physical Design and Verification Engineer

Neuralink

Austin, Texas, United States (On-site)$158K – $243K Yearly
Physical Design Engineering
ASIC Design
RTL-to-GDSII
Physical Design
2w agoCerebras logoCE

Design Verification Engineer- Tile

Cerebras

United States (Remote)$120K – $240K Yearly
Design Verification
Hardware Engineering
SystemVerilog
UVM
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