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System Verilog Jobs in United States

Browse 65 System Verilog jobs in United States on Inference Jobs.

41-60 of 65 jobs
2w agoNVIDIA logoNV

ASIC Clocks Design Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100K – $166.8K Yearly
ASIC Design Engineer
Clock Design Engineer
RTL Design
Verilog
4d agoEtched logoET

DFT Intern

Etched

San Jose, California, United States (On-site)
DFT Engineering
ASIC Design
DFT
Verilog
2w agoEtched logoET

Emulation Software Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
Embedded Software
C++
Linux
2w agoNVIDIA logoNV

Senior Cache Coherency Architect

NVIDIA

Santa Clara, California, United States (On-site)$184K – $287.5K Yearly
Cache Coherency Architect
Interconnect Architecture
Cache Coherency
AXI
2w agoNVIDIA logoNV

Senior CAD Infrastructure Development Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
CAD Engineering
VLSI
C++
Python
3d agoCoreWeave logoCO

Senior Firmware Engineer, FPGA

CoreWeave

New York, United States (On-site)$182K – $242K Yearly
Firmware Engineering
FPGA Development
FPGA
Intel/Altera Quartus
3d agoOpenAI logoOP

Senior RTL Engineer, Interconnect Design

OpenAI

San Francisco, California, United States (Hybrid)$225K – $445K Yearly
RTL Engineering
SoC Design
RTL Design
Verilog
2w agoNVIDIA logoNV

Senior Software R&D Engineer, Digital Logic Synthesis

NVIDIA

Santa Clara, California, United States (On-site)$168K – $264.5K Yearly
EDA Software Development
RTL Synthesis
C++
RTL Synthesis
2w agoNVIDIA logoNV

Software R&D Engineer, RTL Optimization Tools

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $218.5K Yearly
CAD Software Development
EDA Tools Development
C++
RTL Design
6d agoTenstorrent logoTE

Sr. Engineer, CPU RTL Design

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
CPU Design
RTL Design
RISC-V
RTL Design
6d agoTenstorrent logoTE

Sr. Engineer, RTL Implementation

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RTL Implementation
CPU Design
RTL Coding
Verilog
4d agoTenstorrent logoTE

Staff Design for Test STA Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
DFT Engineering
STA Engineering
Design for Test
Static Timing Analysis
4d agoEtched logoET

ASIC Architect

Etched

San Jose, California, United States (On-site)$200K – $265K Yearly
Architecture
ASIC Architecture
ASIC Design
Computer Architecture
4d agoEtched logoET

DFT (Design For Test) Engineer

Etched

San Jose, California, United States (On-site)$150K – $275K Yearly
DFT Engineering
ASIC Design
DFT
Scan Insertion
1w agoNVIDIA logoNV

Principal GPU Memory Architect

NVIDIA

Santa Clara, California, United States (On-site)$272K – $431.3K Yearly
GPU Architecture
Computer Architecture
GPU Architecture
Memory Systems
2w agoNVIDIA logoNV

Senior Architecture Energy Modeling Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
Hardware Engineering
Computer Architecture
Python
C++
1w agoNVIDIA logoNV

Senior Photonic Device Designer

NVIDIA

Santa Clara, California, United States (On-site)$196K – $310.5K Yearly
Photonic Device Design
Optical Engineer
Silicon Photonics
CMOS
2w agoNVIDIA logoNV

Senior Power Analysis and Optimization Engineer, AI-LLM Systems

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
Power Analysis Engineer
AI/ML Engineer
Power Analysis
RTL Design
3w agoTenstorrent logoTE

Staff Engineer, Emulation Technical Lead

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RISC-V
CPU Verification
CPU Verification
Emulation
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