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MEDDPICC Jobs in United States

Browse 42 MEDDPICC jobs in United States on Inference Jobs.

42 jobs
2w agoTenstorrent logoTE

PDK/CAD Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Mixed Signal Design
EDA/PDK Engineering
EDA Tools
PDK
4w agoNeuralink logoNE

Digital IC Design Engineer

Neuralink

Austin, Texas, United States (On-site)$116K – $233.8K Yearly
Brain Interfaces Hardware
Digital IC Design
SystemVerilog
C/C++
1w agoTenstorrent logoTE

Physical Design Engineer, PnR

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design Engineer
PnR Engineer
Physical Design
Place-and-Route
4w agoNeuralink logoNE

Digital IC Design Engineer Intern

Neuralink

Fremont, California, United States (On-site)$35 – $35 Hourly
Digital IC Design
RTL Design
SystemVerilog
C/C++
4w agoNeuralink logoNE

Manufacturing Engineer

Neuralink

Austin, Texas, United States (On-site)$83K – $139K Yearly
Manufacturing Engineering
Mechanical Engineering
3D CAD
SolidWorks
2w agoTenstorrent logoTE

Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design Engineer
ASIC Design
Physical Design
ASIC Design
15h agoGraphcore logoGR

Mechnical Engineer

Graphcore

Austin, Texas, United States (On-site)
Mechanical Engineering
Hardware Engineering
PTC Creo
PCB Design
2w agoNeuralink logoNE

Analog IC Layout Engineer

Neuralink

Fremont, California, United States (On-site)$83K – $139K Yearly
Brain Interfaces Hardware
Analog IC Layout Engineering
Analog IC Layout
Mixed-Signal IC Layout
4w agoNeuralink logoNE

Mechanical Engineer, Implant

Neuralink

Austin, Texas, United States (On-site)$120K – $224K Yearly
Brain Interfaces Hardware
Mechanical Engineering
SolidWorks
CAD
2w agoNeuralink logoNE

Physical Design and Verification Engineer

Neuralink

Austin, Texas, United States (On-site)$158K – $243K Yearly
Physical Design Engineering
ASIC Design
RTL to GDSII
Physical Design
6d agoNeuralink logoNE

Materials Engineer

Neuralink

Fremont, California, United States (On-site)$113K – $209K Yearly
Materials Engineering
Mechanical Engineering
Finite Element Analysis (FEA)
LS-DYNA
7h agoNVIDIA logoNV

Senior Power Integrity Methodology CAD Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
Power Integrity Engineering
CAD Engineering
EMIR Analysis
Rail Analysis
4w agoNeuralink logoNE

Analog IC Design and Verification Engineer

Neuralink

Fremont, California, United States (On-site)$125K – $291K Yearly
Analog IC Design
Mixed-Signal Design
CMOS Circuit Design
Mixed-Signal IC Design

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