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SystemVerilog Jobs in Texas, United States

Browse 18 SystemVerilog jobs in Texas, United States on Inference Jobs.

18 jobs
2 wk. agoEtched logoET

Design Verification Engineer - Internal IP

Etched

Austin, Texas, United States (On-site)$150–275K Yearly
ASIC
Design Verification
UVM
SystemVerilog
1 wk. agoTenstorrent logoTE

Staff Design Verification Engineer, AI HW

Tenstorrent

Austin, Texas, United States (Hybrid)$100–500K Yearly
Design Verification
Hardware Engineering
SystemVerilog
Python
2 wk. agoEtched logoET

Design Verification Engineer - SoC

Etched

Austin, Texas, United States (On-site)$150–275K Yearly
ASIC Design Verification
SoC Verification
SystemVerilog
Python
2 hr. agoTenstorrent logoTE

Staff Engineer, Emulation Technical Lead

Tenstorrent

Austin, Texas, United States (Hybrid)$100–500K Yearly
RISC-V
CPU Verification
CPU Verification
Emulation
4 wk. agoNVIDIA logoNV

ASIC Verification Engineer

NVIDIA

Austin, Texas, United States (Hybrid)$116–189.8K Yearly
ASIC Verification
Hardware Engineering
ASIC Verification
SystemVerilog
3 wk. agoNeuralink logoNE

Digital IC Design Engineer

Neuralink

Austin, Texas, United States (On-site)$116–233.8K Yearly
Brain Interfaces Hardware
Digital IC Design
SystemVerilog
C/C++
4 wk. agoNVIDIA logoNV

ASIC Design Engineer - Hardware

NVIDIA

Austin, Texas, United States (Hybrid)$116–218.5K Yearly
ASIC Design Engineering
Hardware Engineering
RTL Design
Verilog
4 wk. agoNVIDIA logoNV

Senior ASIC Verification Engineer

NVIDIA

Austin, Texas, United States (Hybrid)$136–264.5K Yearly
ASIC Verification
SoC Verification
SystemVerilog
UVM
3 wk. agoNVIDIA logoNV

ASIC Design Verification Engineer - New College Grad 2026

NVIDIA

Austin, Texas, United States (On-site)$116–189.8K Yearly
ASIC Verification
Design Verification
SystemVerilog
UVM
2 hr. agoOpenAI logoOP

Hardware Tools Engineer

OpenAI

United States (Remote)$225–445K Yearly
Hardware Engineering
Software Engineering
Rust
C++
2 wk. agoOpenAI logoOP

Design Verification Engineer

OpenAI

San Francisco, California, US or Remote (Worldwide)$226–445K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog
3 wk. agoTenstorrent logoTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100–500K Yearly
CPU Engineering
Hardware Engineering
RISC-V
RTL Design
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