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Gate Level Verification Jobs

Browse 154 Gate Level Verification jobs on Inference Jobs.

21-40 of 154 jobs

2dD-

Analog IC Design Intern

d-Matrix

Santa Clara, California, United States (Hybrid)$30 – $60 Yearly
3wNV

Low Power ASIC Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100k – $189.8k Yearly
3dGR

Silicon Physical Design Engineer

Graphcore

Bristol, England, United Kingdom (Hybrid)
3dNV

Senior FC Verification Engineer

NVIDIA

Yokneam Ilit, Northern District, Israel (On-site)
5dNV

RTL Design Engineer, DFT

NVIDIA

Yokneam Ilit, Northern District, Israel (On-site)
4wNV

Formal Equivalence Checking Methodology Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $264.5k Yearly
2wOP

RTL & Co-design Engineer (junior)

OpenAI

San Francisco, California, United States (Hybrid)$250k – $460k Yearly
4dNV

Manager, Chip Design

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
3wNV

DFT ATPG Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
2wNV

Compiler Verification Engineer, Compute Performance – GPU

NVIDIA

Austin, Texas, United States (On-site)$140k – $224.3k Yearly
2wVE

Project Manager

Vertiv

Huntsville, Alabama, United States (On-site)
5dNV

ASIC Design Engineer, Hardware Tools and Methodology Development

NVIDIA

Austin, Texas, United States (Hybrid)$116k – $218.5k Yearly
3wVE

DVT Engineer

Vertiv

Westerville, Ohio, United States (On-site)
3wTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100k – $500k Yearly