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AI HW/SW Co-Design Jobs

Explore AI HW/SW Co-Design roles on Inference Jobs and apply today.

2mo agoD-

Digital Design Engineer, Micro-Architect, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$180K – $300K Yearly
R&D - HW Silicon Design
ASIC Design
Micro-architecture
RTL Design
4d agoNV

Senior AI and LLM Engineer

NVIDIA

California, United States (Hybrid)$184K – $356.5K Yearly
AI Engineering
Machine Learning Engineering
AI
LLM
4w agoTE

Sr. RTL Design Engineer - Tensix

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
RTL Design
Hardware Engineering
RTL Design
Microarchitecture
3w agoNV

Software Manager - NVOS

NVIDIA

Yokneam Illit, Northern District, Israel (Hybrid)
Software Engineering Management
Software Development
NVOS
SONiC OS
1mo agoOP

Forward Deployed Engineer - Semiconductor

OpenAI

San Francisco, California, United States (Hybrid)$162K – $302K Yearly
Forward Deployed Engineering
Solutions Engineering
Semiconductor
Chip Design
3mo agoTE

SoC Top-Level Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
SoC Engineering
SoC Physical Design
Floorplanning
3mo agoTE

Staff IP Product Engineer, AI Processor

Tenstorrent

Toronto, Ontario, Canada (On-site)$100K – $500K Yearly
IP Product Engineering
ASIC Design
AI Processors
RISC-V
4w agoTE

Power Architect, AI Data Center Chiplets

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Architecture
Hardware Engineering
Power Management
SoC Power Architecture
1mo agoNV

Principal SoC Architect - Hardware

NVIDIA

Westford, Massachusetts, United States (On-site)$272K – $431.3K Yearly
Hardware Architecture
SoC Architecture
SoC Architecture
ASIC Design
3mo agoNV

Senior High Performance AI Engineer

NVIDIA

Santa Clara, California, United States (On-site)$184K – $356.5K Yearly
AI Engineering
High Performance Computing
C/C++
Python
3w agoET

IC Package Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
Semiconductor Engineering
CoWoS
Substrate Layout