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Tape-out Jobs

Browse 27 Tape-out jobs on Inference Jobs.

27 jobs
2w agoNVIDIA logoNV

Senior Technical Program Manager – VLSI

NVIDIA

Santa Clara, California, United States (On-site)$168K – $322K Yearly
Technical Program Manager
Engineering Program Manager
VLSI
Semiconductor Design
2w agoTenstorrent logoTE

Staff Design for Test STA Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
DFT Engineering
STA Engineering
Design for Test
Static Timing Analysis
2w agoTenstorrent logoTE

Senior Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Engineering
Physical Design
ASIC Design
2w agoTenstorrent logoTE

Technical Program Manager, Architecture

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Architecture TPM
Technical Program Management
RISC-V
SoC
2w agoNVIDIA logoNV

DFT Engineer - Hardware

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
DFT Engineer
Hardware Engineer
DFT
RTL Design
2w agoTenstorrent logoTE

Physical Design Engineer - STA

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
STA
Physical Design
2w agoNVIDIA logoNV

Senior DFT Engineer

NVIDIA

Tel Aviv District, Israel (On-site)
DFT Engineering
ASIC Design
DFT
ATPG
2w agoEtched logoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
2w agoNVIDIA logoNV

Senior DFT ATPG Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
DFT Engineering
ATPG Engineering
DFT
ATPG
3d agoSesame logoSE

Test Engineer, Manufacturing

Sesame

San Francisco, California, United States (On-site)$175K – $280K Yearly
Manufacturing Test Engineer
Test Engineer
Manufacturing Test
PCBA
2w agoTenstorrent logoTE

Staff, Design for Test Engineer (DFT)

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
DFT Engineer
ASIC Design
DFT
ATPG
2w agoTenstorrent logoTE

Static Timing Analysis (STA) Methodology Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
Static Timing Analysis (STA)
PrimeTime
2w agoNVIDIA logoNV

DFT ATPG Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
DFT Engineering
ASIC Design
DFT
ATPG
2w agoTenstorrent logoTE

Design for Test Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
DFT and Test
ASIC Engineering
DFT
RTL
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