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System-Verilog UVM Jobs

Browse 14 System-Verilog UVM jobs on Inference Jobs.

14 jobs
3w agoTenstorrent logoTE

Staff Engineer, SoC RTL Engineer

Tenstorrent

Tokyo Prefecture, Japan (Hybrid)
Architecture
RTL Engineering
Verilog
VHDL
3w agoTenstorrent logoTE

Staff Engineer, CPU Core Verification

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
CPU Core Verification
RISC-V
RISC-V
CPU Verification
1d agoTenstorrent logoTE

Design Verification Lead, AI Hardware

Tenstorrent

Toronto, Ontario, Canada (Hybrid)C$100K – C$500K Yearly
AI Hardware
Design Verification
UVM
SystemVerilog
4w agoNeuralink logoNE

Digital IC Design Engineer Intern

Neuralink

Fremont, California, United States (On-site)$35 – $35 Hourly
Digital IC Design
RTL Design
SystemVerilog
C/C++

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