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Synopsys STAR-RC Jobs

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2mo agoTenstorrent logoTE

Staff Design for Test STA Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
DFT Engineering
STA Engineering
Design for Test
Static Timing Analysis
4d agoNVIDIA logoNV

STA Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
STA Engineer
Physical Design Engineer
Static Timing Analysis
DFT
3mo agoTenstorrent logoTE

Chiplet Physical Design Engineer

Tenstorrent

東京都, Tokyo Prefecture, Japan (Hybrid)
Physical Design
VLSI
Physical Design
Synthesis
2mo agoNVIDIA logoNV

Senior Systems Prototyping Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
FPGA Engineering
ASIC Engineering
FPGA Prototyping
ASIC Design
3mo agoNVIDIA logoNV

Senior Physical Design Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$136K – $264.5K Yearly
Physical Design
ASIC Design
VLSI Physical Design
Place and Route
3w agoNVIDIA logoNV

Physical Design Engineer

NVIDIA

Hsinchu, Hsinchu City, Taiwan (On-site)
Physical Design
VLSI
VLSI
Physical Design
3mo agoNVIDIA logoNV

Senior ASIC Timing Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$168K – $310.5K Yearly
ASIC Engineer
Timing Engineer
Static Timing Analysis (STA)
Physical Design
4w agoTenstorrent logoTE

Design for Test Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
DFT and Test
ASIC Engineering
DFT
RTL
3mo agoGraphcore logoGR

DFT Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
Engineering - Silicon
DFT Engineering
DFT
JTAG
4w agoEtched logoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
1mo agoTenstorrent logoTE

Staff, Design for Test Engineer (DFT)

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
DFT Engineer
ASIC Design
DFT
ATPG
1mo agoTenstorrent logoTE

Physical Design Engineer - STA

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
STA
Physical Design
4w agoNVIDIA logoNV

Senior VLSI CDC Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (Hybrid)
ASIC Engineering
VLSI
SystemVerilog
RTL