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SoC Physical Verification jobs

Explore SoC Physical Verification roles on Inference Jobs and apply today.

81-100 of 325 jobs

NV1w

CPU Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)

$100k – $189.8k Yearly

NV2w

ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)

$116k – $218.5k Yearly

NV2d

ASIC Floorplan Design Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)

$100k – $189.8k Yearly

TE1w

Staff Technical Program Manager, Physical Engineering

Tenstorrent

Santa Clara, California, United States (Hybrid)

$100k – $500k Yearly

NV3w

Senior System Network FW Engineer

NVIDIA

Santa Clara, California, United States (On-site)

$168k – $310.5k Yearly

NV1w

Manager, SOC Modelling

NVIDIA

Santa Clara, California, United States (On-site)

$224k – $431.3k Yearly

NV5d

Senior Digital Design Verification Engineer - Hardware

NVIDIA

Santa Clara, California, United States (On-site)

$136k – $264.5k Yearly

NV1w

DFT Verification Engineer

NVIDIA

Yokneam Ilit, Northern District, Israel (On-site)

NV1w

Software Engineer, SOC Design Methodology

NVIDIA

Santa Clara, California, United States (Hybrid)

$136k – $218.5k Yearly

NV3w

Diag Software Program Manager

NVIDIA

Shenzhen Shi, Guangdong, China (On-site)

TE1w

Principal Engineer, CPU System Microarchitect

Tenstorrent

Austin, Texas, United States (Hybrid)

$100k – $500k Yearly

GR1w

Silicon Verification Lead

Graphcore

Bristol, England, United Kingdom (On-site)

TE5d

Sr. Staff Engineer,Post-Silicon Validation

Tenstorrent

Austin, Texas, United States (Hybrid)

$100k – $500k Yearly

NV4w

Formal Equivalence Checking Methodology Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)

$136k – $264.5k Yearly

NV2w

Senior Mask Layout Design Engineer

NVIDIA

新竹市, Hsinchu City, Taiwan (Hybrid)

GR5d

Silicon Verification Engineer

Graphcore

Bristol, England, United Kingdom (On-site)

D-4d

Analog IC Design Intern

d-Matrix

Santa Clara, California, United States (Hybrid)

$30 – $60 Yearly

NV5d

Senior ASIC Methodology Engineer - LPU Division

NVIDIA

United States (Remote)

$152k – $287.5k Yearly

CE2w

Lead RTL Design Engineer

Cerebras

Sunnyvale, California, United States (Hybrid)

$175k – $275k Yearly

TE1w

Staff Design Verification Engineer, AI HW

Tenstorrent

Toronto, Ontario, Canada (Hybrid)

$100k – $500k Yearly