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On-chip Trace Logic Jobs

Browse 103 On-chip Trace Logic jobs on Inference Jobs.

61-80 of 103 jobs

3wD-

Principal ATE Test Engineer

d-Matrix

Santa Clara, California, United States (Hybrid)$161.3k – $268.8k Yearly
ATE Test Engineering
Hardware Engineering
1wD-

Micro-Architect / RTL Design - CPU, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$196k – $300k Yearly
ASIC Design
CPU Design
1wOP

Reliability/DFX Engineer

OpenAI

San Francisco, California, United States (On-site)$285k – $460k Yearly
ASIC Design
DFX
1wD-

Analog Design Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$155k – $250k Yearly
Analog Design
Hardware Engineering
4wNV

Senior RTL Analysis Methodology Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $264.5k Yearly
ASIC Engineering
Hardware Engineering
2wNV

Senior ASIC Design Engineer

NVIDIA

Canada, Remote, Canada (Hybrid)C$155k – C$245k Yearly
ASIC Design
Digital Design
4wOP

Power Architect

OpenAI

San Francisco, California, United States (On-site)$295k – $445k Yearly
Chip Design
Electrical Engineering
5dNV

Circuit Calibration Design Engineer

NVIDIA

臺北市, Taipei, Taiwan (On-site)
Circuit Design
Electrical Engineering
5dNV

CPU Verification Engineer

NVIDIA

Bengaluru, Karnataka, India (On-site)
ASIC Verification
Computer Architecture
5dNV

RTL Design Engineer, DFT

NVIDIA

Yokneam Ilit, Northern District, Israel (On-site)
ASIC Design
DFT Engineering
1wD-

Technical Program Manager - Hardware/Systems, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$196k – $300k Yearly
Hardware Engineering
Program Management
3wNV

Senior Package Layout Engineer - Hardware

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $258.8k Yearly
ASIC Design
Electrical Engineering
2wTE

SoC Top-Level Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100k – $500k Yearly
Hardware Engineering
Physical Design
2dD-

Analog IC Design Intern

d-Matrix

Santa Clara, California, United States (Hybrid)$30 – $60 Yearly
Analog IC Design
Electrical Engineering
4dNV

Senior Memory Mask Designer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
IC Layout
Memory Design
4dNV

Circuit Design Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Circuit Design
1wCE

Senior/Staff- Engineer: Post Silicon- Bring Up

Cerebras

Bengaluru, Karnataka, India (On-site)$175k – $275k Yearly
ASIC Engineering
Hardware Engineering
5dNV

Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Santa Clara, California, United States (On-site)$168k – $310.5k Yearly
ASIC Design
Electrical Engineering
3dNV

DFT Verification Engineer

NVIDIA

臺北市, Taipei, Taiwan (On-site)
ASIC Verification
Design Verification
1wCE

Staff Hardware Diagnostics Engineer

Cerebras

Sunnyvale, California, United States (On-site)$150k – $260k Yearly
Embedded Systems Engineering
Firmware Engineering

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Hardware EngineeringASIC DesignElectrical EngineeringSilicon EngineeringRTL DesignSemiconductor EngineeringVLSI DesignTest EngineeringASIC EngineeringASIC Verification