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On-Chip Clocking Networks Jobs

Browse 134 On-Chip Clocking Networks jobs on Inference Jobs.

81-100 of 134 jobs

1wNV

Senior Custom Silicon Design Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Hardware Engineering
1wCE

AI Silicon Physical Design Engineer

Cerebras

California, United States (Remote)$150k – $250k Yearly
ASIC Design
Physical Design Engineering
1wCE

Electrical Engineer

Cerebras

Sunnyvale, California, United States (On-site)$150k – $260k Yearly
Electrical Engineering
Electronic Engineering
6dTE

Staff Analog Design Engineer

Tenstorrent

United States (Remote)$100k – $500k Yearly
Analog Design
Hardware Engineering
1wNV

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $264.5k Yearly
ASIC Design
ASIC Physical Design
1wNV

Manufacture System Design Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
Hardware Engineering
Manufacturing Engineering
2wGR

Silicon Logical Design Engineer - Bengaluru

Graphcore

Bengaluru, Karnataka, India (On-site)
ASIC Design
Hardware Engineering
2wD-

Micro-Architect / RTL Design - CPU, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$196k – $300k Yearly
ASIC Design
CPU Design
1wNV

Senior Memory Mask Designer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
IC Layout
Memory Design
1wNV

Physical Design Engineer

NVIDIA

新竹市, Hsinchu City, Taiwan (On-site)
ASIC Design
Hardware Engineering
1wNV

Circuit Design Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Circuit Design
2wNV

ASIC Physical Design and Timing Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116k – $218.5k Yearly
ASIC Engineer
ASIC Physical Design Engineer
1wNV

Senior SoC Power Architect

NVIDIA

Santa Clara, California, United States (On-site)$152k – $287.5k Yearly
Computer Architecture
Electrical Engineering
1wNV

Memory Mask Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
Hardware Engineering
IC Layout
1wNV

Senior VLSI Integration Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (Hybrid)
ASIC Engineering
Hardware Engineering
1dTE

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent

United States (Remote)$100k – $500k Yearly
ASIC Physical Design
Mixed Signal Design
1wCE

CoDesign & NextGen - New College Grad

Cerebras

Sunnyvale, California, United States (On-site)$145k – $155k Yearly
Hardware Engineer
Kernel Development
1wTE

Physical Design Engineer - STA

Tenstorrent

Austin, Texas, United States (Hybrid)$100k – $500k Yearly
ASIC Design
Hardware Engineering
1wCE

3D Physical Design Engineer

Cerebras

Sunnyvale, California, United States (On-site)$150k – $270k Yearly
3D Integration
ASIC Design
3wNV

ASIC Physical Design CAD, Timing Constraint and Analysis

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Engineering
ASIC Physical Design

Related searches

Hardware EngineeringASIC DesignPhysical DesignVLSI DesignSemiconductor EngineeringSilicon EngineeringASIC Physical DesignElectrical EngineeringRTL DesignSoC Design