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Low-Level Protocol Design Jobs

Explore Low-Level Protocol Design roles on Inference Jobs and apply today.

3mo agoCE

Senior Runtime Engineer

Cerebras

Sunnyvale, California, United States (On-site)
Software Engineer
Distributed Systems
C/C++
Distributed Systems
1mo agoTE

Network ASIC Designer

Tenstorrent

North America (Remote)$100K – $500K Yearly
Architecture
ASIC Design
ASIC Design
Network Architecture
3w agoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
3w agoET

Physical Design Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
Physical Design
Physical Design
ASIC
2w agoNV

Logic Design Engineer, CPU Core

NVIDIA

Yokne'am, Northern District, Israel (On-site)
ASIC Design
Logic Design
Logic Design
Microarchitecture
3w agoTE

Design for Test Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
DFT and Test
ASIC Engineering
DFT
RTL
2mo agoNV

Software Design Engineer - SONiC Group

NVIDIA

Raanana, Central District, Israel (On-site)
Software Engineering
Network Engineering
C++
Python
4d agoNV

Software Engineer, DOCA

NVIDIA

Yokne'am, Northern District, Israel (On-site)
Software Engineering
Embedded Software
C/C++
Linux
3w agoTE

Software Engineer, Metal Runtime (API & Abstractions)

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Software Engineering
Embedded Software
C
C++
2mo agoNV

Senior Circuit Design Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
Circuit Design
Hardware Engineering
Circuit Design
Spice Simulations
2w agoNV

GPU Power Analysis Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Hardware Engineering
Python
C++
4w agoNV

Software Team Manager

NVIDIA

Raanana, Central District, Israel (On-site)
Software Engineering Management
Engineering Management
Python
C++
6d agoNV

Physical Design Engineer

NVIDIA

Yokne'am, Northern District, Israel (On-site)
Physical Design
VLSI
Physical Design
RTL-To-GDS
4w agoTE

Staff, Design for Test Engineer (DFT)

Tenstorrent

Bengaluru, Karnataka, India (Hybrid)
DFT Engineer
ASIC Design
DFT
ATPG