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High-level Synthesis Jobs

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2w agoNVIDIA logoNV

Senior Deep Learning Scientist, Speech Synthesis

NVIDIA

Ho Chi Minh City, Ho Chi Minh City, Vietnam (On-site)
Deep Learning Scientist
Speech Synthesis
Python
PyTorch
2mo agoNVIDIA logoNV

Senior Implementation Methodology Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
Physical Design
VLSI
Logic Design
Physical Design
3mo agoNVIDIA logoNV

Implementation Methodology Engineer - GPU

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
VLSI Engineering
Hardware Engineering
Synthesis
Formal Equivalence Checking
3mo agoTenstorrent logoTE

Chiplet Physical Design Engineer

Tenstorrent

東京都, Tokyo Prefecture, Japan (Hybrid)
Physical Design
VLSI
Physical Design
Synthesis
2mo agoNVIDIA logoNV

Senior Systems Prototyping Engineer

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
FPGA Engineering
ASIC Engineering
FPGA Prototyping
ASIC Design
3mo agoNVIDIA logoNV

Senior ASIC Timing Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$168K – $310.5K Yearly
ASIC Engineer
Timing Engineer
Static Timing Analysis (STA)
Physical Design
6d agoNeuralink logoNE

Physical Design and Verification Engineer

Neuralink

Austin, Texas, United States (On-site)$158K – $243K Yearly
Physical Design Engineering
ASIC Design
RTL to GDSII
Physical Design
3mo agoNVIDIA logoNV

Senior ASIC RTL Integration and Netlisting Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
ASIC Design Engineer
Physical Design Engineer
ASIC
RTL Integration
1mo agoNVIDIA logoNV

Physical Design Backend Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
Physical Design
Backend Engineering
Physical Design
RTL2GDS
1mo agoEtched logoET

RTL Design Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
RTL Design
RTL Development
3mo agoNVIDIA logoNV

ASIC RTL Integration and Netlisting Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100K – $189.8K Yearly
ASIC Engineering
Physical Design
ASIC
RTL
3mo agoCerebras logoCE

Lead RTL Design Engineer

Cerebras

Sunnyvale, California, US$175K – $275K Yearly
ASIC Design
RTL Design
RTL Design
ASIC
1mo agoNVIDIA logoNV

Senior Logic Design Engineer, CPU Core

NVIDIA

Yokne'am, Northern District, Israel (On-site)
Logic Design
CPU Design
Logic Design
Microarchitecture
1mo agoNVIDIA logoNV

Senior Chip Design Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
Chip Design
Hardware Engineering
RTL Design
Micro-architecture